MOTM

>>>>
Now, if you want to be able to set the delay time such that it is 
longer than the time between incoming gates, that looks like it's 
going be very difficult.  It's an interesting problem and I'm going 
to look into it, but my intuition tells me that no matter how it's 
designed there is going to be a limit on the number of gates delayed 
(I'm thinking at least two flip-flops per gate).  It might be easier 
to use some sort of PAL or uP, which is beyond my ability.
<<<<

In terms of traditional envelope generator-type gate delaying (which 
was the thrust of the initial conversation), you want to delay the 
incoming positive going transition (a timer, or just an RC/comparator 
arrangement). The incoming negative going transition is not delayed, 
but sends the envelope into final decay as always. There is typically 
no attempt to maintain the input gate's on state time.

Moe

At 7:19 PM +0100 09/18/01, sikorsky wrote:
>
>hello all,
>what have i started..?
>fortunately i seem to have stumbled across a brand d schematic which looks
>very simple and will bridge the gap until the texas cavalry arrives - after
>all, i don't really need a gate delay, it's just part of my learning
>process - by the time i've learnt enough dil semiconductors will be worth
>more than diamonds anyway...

Is the d for dummkopf?? ;)

(Everything I know about German people is from Hogans Heroes :)

I've seen the same schematic.  It's just a sequential timer -- the first
timer sets the delay time, the second timer sets the length of the gate
out.  It does not preserve the pulse width of the incoming gate, in fact,
it treats an incoming gate as a trigger -- completely ignoring the trailing
edge.  As such, it should be called a trigger delay.  Nor does it recognize
incoming triggers after the first timer is still armed.


At 5:48 PM +0000 09/18/01, mate_stubb@... wrote:
>
>In terms of traditional envelope generator-type gate delaying (which
>was the thrust of the initial conversation), you want to delay the
>incoming positive going transition (a timer, or just an RC/comparator
>arrangement). The incoming negative going transition is not delayed,
>but sends the envelope into final decay as always. There is typically
>no attempt to maintain the input gate's on state time.

So if the trailing edge of the incoming gate arrives before the delay ends,
there is no output.  Off the top of my head, I'd say you can do that with a
4047.  The D___ module doesn't do that.

Anyway, does anyone know of a good way to get a regulated 5V
from a 15V supply??  Perhaps we can agree upon a MOTM standard that can be
used for all logic modules.  Then we can start breadboarding :)  I get the
feeling Paul S. doesn't like the 7805.

> I've seen the same schematic.  It's just a sequential timer -- the first
> timer sets the delay time, the second timer sets the length of the gate
> out.  It does not preserve the pulse width of the incoming gate, in fact,
> it treats an incoming gate as a trigger -- completely ignoring the
trailing
> edge.  As such, it should be called a trigger delay.  Nor does it
recognize
> incoming triggers after the first timer is still armed.

hello all,
interesting, but since it's only going to cost around \ufffd2 in parts i'm going
to give it a go
then i can also learn how to buffer an LED properly...

cheers
paul b