MOTM

"Brousseau, Paul E (Paul)" wrote:
> 
> Do you suggest that the module use digital memory with an analog
> VC-controlled clock?  That sounds interesting to me, albiet perhaps a bit
> tricky.  I wonder what kind of different artifacts would be produced...

Yes. I guess the trick is using a high enough sample rate on the top-end
to compensate for the low end. The RPS-10 has a rotary switch for
choosing 
between  0-200ms, 200-400ms, and 400 to 800ms. After all, what is the
top-end frequency of an analog delay. The sample rate doesn't have to be
that great. Add a low pass filter tracking the input voltage to hide the
artifacts.
> 
> In another e-mail, you mentioned using a second delay line.  Apparently (if
> I remember the discussion on SDIY correctly) you need to do this on an
> analog delay as well, because while the caps (samples) in one line are
> charging, you need the second line to discharge.  I suggested upping this to
> more lines (3 or 4) but I don't think anyone commented.  I'm not sure what
> benefit it might have.
> 
I think Aderton was refering to the fact that the minimal delay was
something
like 1ms (which may only be the case for eighties delays/sample rates).
If
you delay the original signal by this much you get true thru zero
flanging.

Though to be honest, I've never heard an analog or digital flanger sound
as good as some tape based flanging effects. But I don't have a clue as
to why this is true.

Thomas