Do you suggest that the module use digital memory with an analog
VC-controlled clock? That sounds interesting to me, albiet perhaps a bit
tricky. I wonder what kind of different artifacts would be produced...
In another e-mail, you mentioned using a second delay line. Apparently (if
I remember the discussion on SDIY correctly) you need to do this on an
analog delay as well, because while the caps (samples) in one line are
charging, you need the second line to discharge. I suggested upping this to
more lines (3 or 4) but I don't think anyone commented. I'm not sure what
benefit it might have.
--PBr
> -----Original Message-----
> From:Thomas Hudson [SMTP:thudson@...]
> Sent:Wednesday, April 19, 2000 5:04 PM
> To:motm@egroups.com
> Subject:Re: [motm] Delay Module.. Digital bad?
>
>
> Duh. All my previous rambling had a point I never made.
> I wonder the best of both worlds (or good parts from each)
> couldn't be had if you designed a digital circuit based
> on analog/bbd ideas. Don't do anything DSP based. Memory
> can be treated as a bbd.
>