> For example, if input of a'730 is gates of a keyboard and some
> triplets with ties are played, - will there be /7 output at all? in
> other words - how many clock pulses is needed for a particular divisor
> to successfully give an output and how long it will stay on if the
> input clock suddenly changes or turns off?
There are 3 important things to understand about the '730:
a) the ∗width∗ of the input pulse is not important.
b) the output pulses will ∗always∗ be 50% (+-1 clock) square waves
c) for odd (or fractional) divides, the algorithm in the PIC counts based on
an "even/odd pulse count" scheme
Refer to this 'drawing' showing the first 7 outputs of the '730 from my old
HP logic Analyzer:
www.synthtech.com/motm/m730_out.jpg
Looking at your /7 example, you will see that you are correct: for the first
4 ∗full cycles∗ of the input clock, there is no output. Then, the output is
high for the last 3 cycles. This is the even/odd scheme (4, then 3 = 7
total).
Look at /3, /4 and /5. Notice all three go high after ∗2∗ clocks (the 'even'
count').
The other thing to note (and this is a good thing!) is that all counting is
synchronous. If you look at the /2, /4 and /8 signals, see that all 3
transition from high-to-low at the same time. This is to expected since they
are all powers of 2. But we can ∗also∗ do this for /3 and /6 using this
pulse-counting technique.
What this means is that is ∗very easy∗ to get patterns locked and syncopated
from 1 master clock. There have been other divider modules in the past, but
none that I am aware of that have this synchronous pulse-counting with both
odd and even divisors, and ∗also∗ with 1/2 divisors.
When you are in 1/2 divisors mode (say /7.5) this means the algorithm
switches from counting full clock cycles (high-to-low-back to high) to
counting each 1/2 cycle of the input clock (low-to-high and high-to-low).
Paul S.