http://www.ear-group.net/model_23.htmlPlan B has a 'traditional' ASR coming out (analog, 3 stages, no delay). The
link has a few sound samples and graphs/charts.
I think some folk are confused about the "sample rate" versus the "shift
rate".
In this module, it's the ∗same thing∗.
If you feed in a pulse to the CLK IN (or, at the rate of the INT CLK):
a) the voltage at the INPUT jack is sampled by the 14-bit A/D converter
b) the ARM uP get an interrupt from the A/D ("Hey, I've finished sampling
now!"), and then updates the 4 outputs based on the presence or absence of
delay memory.
So, if the clock is 1Hz, then once a second, the input is sampled AND all
the outputs get updated (this happens quite quickly, on the order of a few
1000ths of a second).
What makes the '102 unique is that since there is no analog capacitor to
charge up/hold in-between clocks, we can:
a) clock the ASR ∗really fast∗, limited really to the ARM execution speed
and the time it takes the serial SPI buss to shuffle the data from the ADC
out to the 4 DACs. I am guessing this will wind up around 2Khz
b) there is no "droop" error (drop in output voltage over time)
c) the ARM has enough internal RAM so that we can "play around" with the
samples, and make a sort of 'reverb for CVs'
Paul S.