On 2/6/08, Paul Schreiber put forth:
> > Could you please explain that again?? For analogue S&H and ASR
> > modules, the sampling rate is the same as the step clock, where the
> > delay time is only limited by droop. How does that relate to the
> > frequency of code clock in this module??
>
>First, let's expain what exactly a 'shift register' does.
Thank you for enplaning that. While I understand how a shift
register works, you said the "S&H code can be clock at a ∗minimum∗ of
1Khz". That's 60,000 BPM. Which leads to believe that either this
clock driving the "code" is different than the sampling rate, or you
meant something else. Hence my confusion. By "minimum" do you
actually mean maximum, that at a minimum, the fastest it can be
clocked is 1,000 times per second??
>The typical analog ASR has NO DELAY ∗between∗ stages: 1>>2>>3>>4 lets say.
What I meant by "delay" in an analogue ASR is equal to the period of
the clock. A typical use for an ASR is a gate or trigger delay --
when the input goes high, it doesn't appear at whichever output until
that many clock edges later. Too long a "delay" and the cap will
discharge.