> An internal clock out is a popular and easy mod for the MOTM-101, but
> might not be so easy to add to the proposed 102 due to its SMD
> design and possible lack of panel space.
I have decided to replace the dedicated Slow Random output with a CLK OUT
jack.
>
> Also, if there is only one noise output with a knob, wouldn't a more
> extreme setting be equivalent to slow random??
That's the plan :)
> Could you please explain that again?? For analogue S&H and ASR
> modules, the sampling rate is the same as the step clock, where the
> delay time is only limited by droop. How does that relate to the
> frequency of code clock in this module??
First, let's expain what exactly a 'shift register' does.
Everyone has heard of a BBD (bucket-brigade device), and a shift register is
the 'digital' equivalent.
A BBD stores charges, and every clock pulse, every BBD passes it's charge to
the BBD next to it.
A shift register, on every clock, passes it's digital data to the stage
(register) next to it.
So, if I have a 12-stage shift register (or, a BBD with 12 storage cells),
it takes 12 clock pulses for the input
to "appear" at the output. Now every clock pulse, ∗something∗ appears at the
output, and what that ∗something∗
is happens to be what state the input was 12 clock pulses ∗ago∗.
What the MOTM-102 does is make a digital equivalent of a BBD chip. Instead
of storing analog voltages as a charge on a capacitor (BBD),
we digitize the signal and store it into internal RAM of the ARM uC. The
software, every time there is a clock pulse (internal or external), samples
the inputs and THEN shoves all the pre-existing samples "down the line", 1
RAM location at a time.
If you are saying to yourself "Hey, isn't that how a digital delay or
reverb works?" you would be correct :)
The typical analog ASR has NO DELAY ∗between∗ stages: 1>>2>>3>>4 lets say.
So, if I turn it on and load 0.0V into all 4 stages, it get:
0>>0>>0>>0 at the outputs.
If I apply 1V to the input ∗and leave it there∗ for 4 clocks, here is what I
get:
0>>0>>0>>0 a clock occurs!
1>>0>>0>>0 a clock occurs!
1>>1>>0>>0 a clock occurs
1>>1>>1>>0 and so on.......
What makes the MOTM-102 unique is that we can assign a delay (which is
nothing more that ∗adding stages you don't have access to∗) in between the
LAST 3 stages (and with a switch, also to the first stage so that what
follows below does NOT occur!).
So, if I add the case of 1 added stage, I get:
0>>d>>0>>d>>0>>d>>0 when powered up The 'd' is an internal RAM location.
Now, let's assume I have 1V present for 2 clocks, then 2V for 1 clock, then
3V for the rest. OK, here we go!
0>>d>>0>>d>>0>>d>>0 when powered up
1>>d>>0>>d>>0>>d>>0 a clock occurs! (the first 1V is shifted in)
1>>d>>0>>d>>0>>d>>0 a clock occurs! (the second 1V shifted in, the first 1V
is in the 'delay tap')
2>>d>>1>>d>>0>>d>>0 a clock occurs! (now the 2V is in)
3>>d>>1>>d>>0>>d>>0 a clock occurs! (now the 3V is in)
3>>d>>2>>d>>1>>d>>0 a clock occurs!
3>>d>>3>>d>>1>>d>>0 a clock occurs!
3>>d>>3>>d>>2>>d>>1 a clock occurs!
3>>d>>3>>d>>3>>d>>1 a clock occurs!
3>>d>>3>>d>>2>>d>>3 and so on..............
Now, what is REALLY interesting (at least to me) is that in this case, there
is ∗no time∗ that the input sequence (1V, 1V, 2V, 3V) appears on the 4
outputs! We get close (0V, 1V, 2V, 3V), but due to the interaction of the
delay length versus the number of clocks an input is present, this sort of
thing will occur. See, it's a chaotic shift register (worse that a Psycho
Shift Register?)
Also, if I make a table comparing the outs with no delay (ASR) versus 1-tap
delay, it looks REALLY interesting!
CLOCK OUTPUT ASR OUTPUT 1TAP
1 0,0,0,0 0,0,0,0
2 1,0,0,0 1,0,0,0
3 1,1,0,0 1,0,0,0
4 2,1,1,0 2,1,0,0
5 3,2,1,1 3,1,0,0 <---- look, the ASR
has the proper output, the 1tap is off in the weeds :)
6 3,3,2,1 3,2,1,0 <---- close, but no
cigar
7 3,3,3,2 3,3,1,0
8 3,3,3,3 3,3,2,1
9 3,3,3,3 3,3,3,1
10 3,3,3,3 3,3,3,2
11 3,3,3,3 3,3,3,3
Of course, with NO delay, then this is not an issue: every input is copies
and shifted to an output EVERY clock, so nothing is "lost". This will also
be true if there is a 4th added delay: between the sampling and the first
stage, as so:
d>>0>>d>>0>>d>>0>>d>>0
The exercise is left to the reader that adding the delay in front of stage
#1 "preserves" all of the samples, unlike the example described in chaos
mode. I plan to have a switch labelled NORMAL/CHAOS (for lack of a better
term, open for suggestions) that tells the code how to organize the samples
in RAM.
>
> That sounds like a nice feature, as the quantized random voltages of
> the SH-101 and other synths is a popular sound. It would also make
> the "playing chords by loading an ASR" trick much easier. So my
> suggestion for four quantize settings would be chromatic, major,
> minor, and 6-bit.
I'm going to have a JI scale in there :)
>
> On 2/3/08, Richard Brewster put forth:
>>3) I'm trying to understand the delay factor. If this is set to 256 and
>>the input clock is 256 Hz, does this mean that the outputs change once
>>per second, or 256 times per second? If the latter, does this mean that
>>the 2nd tap lags the first by 1 second? The 4th tap would be delayed by
>>3 seconds here? Maybe you can describe it better.
It is more precise to state: the outputs are UPDATED every clock pulse. They
may, or may ∗not∗ change,
based on what the data is at the input relative to the time it was sampled.
Paul S.