Paul Haneberg writes:
>>I've been trying to determine the proper algorithm for a gate and/or
trigger delay.<<
If I were to do it, this is how. When the gate delay module receives the start
of a gate, I'd write a counter into a fifo buffer in memory. The counter is
set to whatever delay time the user selects based on some number of clocks per
second (say 1024 ticks per second). When the gate ends, I'd write a second
count representing the length of the gate into a word right after the first
counter. You could store hundreds of gates this way, not that you need
anywhere that many. When the first counter decrements to zero, you put out a
gate signal and then start decrementing the second gate-time counter. When it
hits zero you close down the gate. Most high-end digital sequencers only have
a resolution of about 1/1024 of a second, so you would use a time resolution
like that to decrement counters and store gate times.
BTW, great Jerusalem rendition.
-Elhardt