There's no "right answer" to how gate and trigger delays should work;
everybody has their own opinion. What follows is my opinion on this
topic.
At 3:56 PM +0000 2003/05/15, paulhaneberg wrote:
>The first question is what happens if the incoming gate ends before
>the delayed gate has been produced (assume a delay of 3 seconds with
>a gate length of 1 second) is the delayed gate still produced at
>the output?
Yes.
>or must the incoming gate be present to enable the
>delayed gate to be produced at the output?
No.
>This leads to the second question. If the delayed gate is to be
>produced at the output even if the incoming gate stops, what happens
>if the key (or other event) is pushed a second time before the
>delayed gate is output?
You get a second gate.
>Should the relationship between the leading
>edgeof the first gate, the trailing edge of the first gate and the
>leading edge of the second gate be preserved?
Yes.
>This is important because it seems to me if multiple events are to
>be all delayed and fed through to the delayed output, the circuit
>must be a sort of 1-bit shift register with the delay control either
>selecting a tap or controlling the clock speed. If multiple events
>are not to be preserved a simple analog circuit involving a
>capacitor for timing and a couple of analog switches will do the job.
Multiple events need to be preserved.
Here's a sneak preview of my logic delay line that also works as a
gate/trigger delay:
http://www.tellun.com/motm/diy/tln774/TLN-774.htmlThis panel mockup is already a little out of date, but the thing does
preserve both edges of a signal and stores multiple events. In my
opinion, that's the only way to go.