>>>>
Now, if you want to be able to set the delay time such that it is
longer than the time between incoming gates, that looks like it's
going be very difficult. It's an interesting problem and I'm going
to look into it, but my intuition tells me that no matter how it's
designed there is going to be a limit on the number of gates delayed
(I'm thinking at least two flip-flops per gate). It might be easier
to use some sort of PAL or uP, which is beyond my ability.
<<<<
In terms of traditional envelope generator-type gate delaying (which
was the thrust of the initial conversation), you want to delay the
incoming positive going transition (a timer, or just an RC/comparator
arrangement). The incoming negative going transition is not delayed,
but sends the envelope into final decay as always. There is typically
no attempt to maintain the input gate's on state time.
Moe