MOTM

On 2/8/08, Paul Schreiber put forth:
>I think some folk are confused about the "sample rate" versus the "shift
>rate".
>
>In this module, it's the *same thing*.
>
>If you feed in a pulse to the CLK IN (or, at the rate of the INT CLK):
>
>a) the voltage at the INPUT jack is sampled by the 14-bit A/D converter
>b) the ARM uP get an interrupt from the A/D ("Hey, I've finished sampling
>now!"), and then updates the 4 outputs based on the presence or absence of
>delay memory.
>
>So, if the clock is 1Hz, then once a second, the input is sampled AND all
>the outputs get updated (this happens quite quickly, on the order of a few
>1000ths of a second).

Thanks for the clarification.  What confused me was the "minimum"
rate of 1KHz, which seemed like either a very slow uP clock or a very
fast sampling clock.