The "inner layers" are for a split ground plane (analog and digital ground, connected at only 1 point via ferrite bead) and a *mostly* dedicated power distribution plane. There are 4 power signals: +5 digital (noisy), +5 analog (clean, from super whiz-bang Linear Tech regulator), and the standard +-15V for the op amps. This is also my 'lifeline' routing layer if the top and bottom are congested. In most power cases, a 'trace' is not used but more of a "polygon" area. My CAD software allows something called a "free-form copper pour" which means I define an outside boundary and the CAD fills the interior with solid copper. In SMT ICs, the power is routed by a via dropped into the power plane area. I will have PDF of this next week. I'm still fitting all the parts in, just had an "Oh S*IT!" moment on a connector orientation and have to re-place the analog section. Paul S.
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MOTM-650 CPU layers
2005-09-18 by Paul Schreiber
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