MOTM

At 7:20 PM +0000 5/16/03, paulhaneberg wrote:
>
>The circuit design I had worked out didn't use a current mirror or
>dual pot, it compared the voltage level of a charging cap (actually
>two of them) to a level set by a combination of input voltage and
>pot setting.  The first cap started charging on the gate leading
>edge, the second on the gate trailing edge.

I think I understand.  You used two discrete comparators rather than
the built-in comparators of two timer chips.

>I think a 1 bit delay line is in fact the way to go.  I haven't
>decided yet whether to have multiple clock ranges or a long delay
>line with the selection of the tap on a log scale.  I would agree
>that an 8 bit or perhaps 10 or 12 bit delay line clocked at roughly
>1Khz would be a good idea for delaying control voltages.  In fact I
>think there should be a whole family of time delay based modules.

Imho, varying the clock speed would give you a finer range of
adjustment.  I'm sure there are schematics for "real" digital delays
on the web -- you would just have to make it DC-coupled.  You might
be able to rip the blocking caps out of an existing delay.

My thinking is if someone is going go through all of the work of
building a digital delay module, they might as well make it at least
8-bit.  I'm no digital designer, but compared to the cost of the
panel hardware, any increase in cost would be insignificant.

>  Perhaps the legendary 200 series?

Too bad there is a 100, 101, and 110, otherwise he could have named a
digital series 001, 010, 110, etc.  :)