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Gate and Trigger Delays

2003-05-15 by paulhaneberg

I've been trying to determine the proper algorithm for a gate and/or 
trigger delay.  Heres the dilemma.
I assume that the length of the gate should be preserved, so the 
trailing edge of the gate needs to be delayed by an amount equal to 
the leading edge.  Delaying a trigger is easier since its just a 
very short pulse, but if a module is to allow for the delay of both 
gates and triggers, the delay time for the gate and the trigger must 
be the same with reasonable precision.
The first question is what happens if the incoming gate ends before 
the delayed gate has been produced (assume a delay of 3 seconds with 
a gate length of 1 second)  is the delayed gate still produced at 
the output?  or must the incoming gate be present to enable the 
delayed gate to be produced at the output?
This leads to the second question.  If the delayed gate is to be 
produced at the output even if the incoming gate stops, what happens 
if the key (or other event) is pushed a second time before the 
delayed gate is output?  Should the relationship between the leading 
edgeof the first gate, the trailing edge of the first gate and the 
leading edge of the second gate be preserved?
This is important because it seems to me if multiple events are to 
be all delayed and fed through to the delayed output, the circuit 
must be a sort of 1-bit shift register with the delay control either 
selecting a tap or controlling the clock speed.  If multiple events 
are not to be preserved a simple analog circuit involving a 
capacitor for timing and a couple of analog switches will do the job.
I realize this could be implemented using a PIC and in fact I think 
one MOTMer has already done this, but even if a PIC is used the 
question is still valid as the algorithm must still be worked out.
I'd certainly like to hear everyones opinion on this one.

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