NETS
2011-02-19 by Randy S.
Whats the concept of "nets" in all this pcb creation process?
Randy
Randy
Thread
NETS
Re: [Homebrew_PCBs] NETS
2011-02-19 by Adam Shea
A net is just a list of connected pins. This is the primary input from
the Schematic capture program to the PCB. They mainly serve as guides
for what pins need to be connected by copper.
--Adam Shea.
the Schematic capture program to the PCB. They mainly serve as guides
for what pins need to be connected by copper.
--Adam Shea.
On 02/18/11 19:42, Randy S. wrote:
> Whats the concept of "nets" in all this pcb creation process?
>
> Randy
>
>
>
>
>
> ------------------------------------
>
> Be sure to visit the group home and check for new Links, Files, and Photos:
> http://groups.yahoo.com/group/Homebrew_PCBsYahoo! Groups Links
>
>
>
Re: [Homebrew_PCBs] NETS
2011-02-19 by rrrydman@aol.com
Hi Randy,
My understanding of nets is that they are "networks'. A trace that goes from one pin to another is a net. Another third pin to a different pin is another net. Either of these nets might branch to yet another pin and that would still be on that respective net. An entire board will have many nets. Starting a new trace and connecting it to an existing net will require you to specify the net number you are connecting to. This can be determined by puting the cursor on the intended net and clicking and inspecting properties of that net .. or it might be shown somewhere on the screen for that selected net. ummmm hope this helps.
Bob R.
-----Original Message-----
From: Randy S. <rj3819@...>
To: Homebrew_PCB <homebrew_pcbs@yahoogroups.com>
Sent: Fri, Feb 18, 2011 5:42 pm
Subject: [Homebrew_PCBs] NETS
Whats the concept of "nets" in all this pcb creation process?
Randy
[Non-text portions of this message have been removed]
My understanding of nets is that they are "networks'. A trace that goes from one pin to another is a net. Another third pin to a different pin is another net. Either of these nets might branch to yet another pin and that would still be on that respective net. An entire board will have many nets. Starting a new trace and connecting it to an existing net will require you to specify the net number you are connecting to. This can be determined by puting the cursor on the intended net and clicking and inspecting properties of that net .. or it might be shown somewhere on the screen for that selected net. ummmm hope this helps.
Bob R.
-----Original Message-----
From: Randy S. <rj3819@...>
To: Homebrew_PCB <homebrew_pcbs@yahoogroups.com>
Sent: Fri, Feb 18, 2011 5:42 pm
Subject: [Homebrew_PCBs] NETS
Whats the concept of "nets" in all this pcb creation process?
Randy
[Non-text portions of this message have been removed]
Re: [Homebrew_PCBs] NETS
2011-02-19 by Piers Goodhew
It may just be me, but I found the easiest way to understand nets was from the commonest one: "GND" - the reason for naming them is you can have things connected in your layout which you don't have to show in the schematic (and ground, again, is a great example of why you might want to do that).
PG
PG
On 19/02/2011, at 4:24 PM, rrrydman@... wrote:
>
> Hi Randy,
> My understanding of nets is that they are "networks'. A trace that goes from one pin to another is a net. Another third pin to a different pin is another net. Either of these nets might branch to yet another pin and that would still be on that respective net. An entire board will have many nets. Starting a new trace and connecting it to an existing net will require you to specify the net number you are connecting to. This can be determined by puting the cursor on the intended net and clicking and inspecting properties of that net .. or it might be shown somewhere on the screen for that selected net. ummmm hope this helps.
> Bob R.
>
> -----Original Message-----
> From: Randy S. <rj3819@...>
> To: Homebrew_PCB <homebrew_pcbs@yahoogroups.com>
> Sent: Fri, Feb 18, 2011 5:42 pm
> Subject: [Homebrew_PCBs] NETS
>
> Whats the concept of "nets" in all this pcb creation process?
>
> Randy
>
> [Non-text portions of this message have been removed]
>
>
RE: [Homebrew_PCBs] NETS
2011-02-19 by Dave
Not sure how far back NETS go but I encountered them with Spice. Basically a
net or netlist is an abstract representation of a circuit. It contains the
electrical properties of the circuit, so a list of the components and how
they are connected, but has no information about how they are physically
laid out. In thaematical terms it contains the topology of the circuit.
I first encountered it with various Spice programs, but not sure if it
originated with Spice or if it predates it in some way.
Dave
net or netlist is an abstract representation of a circuit. It contains the
electrical properties of the circuit, so a list of the components and how
they are connected, but has no information about how they are physically
laid out. In thaematical terms it contains the topology of the circuit.
I first encountered it with various Spice programs, but not sure if it
originated with Spice or if it predates it in some way.
Dave
> -----Original Message-----
> From: Homebrew_PCBs@yahoogroups.com
> [mailto:Homebrew_PCBs@yahoogroups.com] On Behalf Of rrrydman@...
> Sent: 19 February 2011 05:25
> To: Homebrew_PCBs@yahoogroups.com
> Subject: Re: [Homebrew_PCBs] NETS
>
>
>
> Hi Randy,
> My understanding of nets is that they are "networks'. A trace
> that goes from one pin to another is a net. Another third pin
> to a different pin is another net. Either of these nets might
> branch to yet another pin and that would still be on that
> respective net. An entire board will have many nets. Starting
> a new trace and connecting it to an existing net will require
> you to specify the net number you are connecting to. This can
> be determined by puting the cursor on the intended net and
> clicking and inspecting properties of that net .. or it
> might be shown somewhere on the screen for that selected net.
> ummmm hope this helps. Bob R.
>
>
>
>
>
>
>
>
> -----Original Message-----
> From: Randy S. <rj3819@...>
> To: Homebrew_PCB <homebrew_pcbs@yahoogroups.com>
> Sent: Fri, Feb 18, 2011 5:42 pm
> Subject: [Homebrew_PCBs] NETS
>
>
>
>
>
> Whats the concept of "nets" in all this pcb creation process?
>
> Randy
>
>
>
>
>
>
>
>
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Be sure to visit the group home and check for new Links,
> Files, and Photos:
> http://groups.yahoo.com/group/Homebrew_PCBsYahoo! Groups Links
>
>
>
>
Re: NETS
2011-02-19 by designer_craig
Randy,
In any electronic circuit, the pins of the various components that are
connected together are called a net. Generally a net connects two or
more component pins and a circuit or schematic design is a collection of
one or more nets. A schematic is just a graphical way of representing
what component pins must be connected together for the design. The
schematic capture program (editor) will assign a net name to each of the
unique nets in the design. Most programs assign the nets a numeric name
but usually allow the user to change this to something more useful like
"reset" or "clock" etc. Debugging a design is much
easier if all the nets have some functional name. Most of the schematic
capture packages that I have used allow you to draw a stub of a wire to
a component pin and assign it a net name. All stubs that have the same
name are on the same net and connected even though there is no direct
graphics line on the schematic. This is a "connect by name"
feature and is quite useful in complex designs. Things get a little
more complex when you have busses, which are sort of a short hand for a
collection of similar named nets or have a hierarchical schematic. In
high-end programs nets can be assigned various properties in addition to
just a name and are used to guide the PCB layout process. Things like
the maximum number of vias, trace width, trace spacing, layer and
propagation delay are common. With today's high-speed processors
and memory impedance control and trace propagation delay matching are
critical to proper operation. Once the design is in the PCB layout
stage these net properties can be used to guide both manual and
auto-routing of the board, they are also used for post layout design
rule checking.
Once in the PCB layout program each net becomes a copper tract (or
plane) that connects the component pins assigned to that net.
Most schematic packages will let you output a "net list" which is
usually a text file containing a list of nets in the design and the
component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
layout packages will accept a text file net list as input.
In additon to a list of NET's the PCB layout software needs to know what
footprint to use for a particular component. Generally, but not always,
the footprint name is attached as a property to the component symbol
used when drawing the schematic and provided to the PCB program when the
PCB program reads in the schematic.
Craig
In any electronic circuit, the pins of the various components that are
connected together are called a net. Generally a net connects two or
more component pins and a circuit or schematic design is a collection of
one or more nets. A schematic is just a graphical way of representing
what component pins must be connected together for the design. The
schematic capture program (editor) will assign a net name to each of the
unique nets in the design. Most programs assign the nets a numeric name
but usually allow the user to change this to something more useful like
"reset" or "clock" etc. Debugging a design is much
easier if all the nets have some functional name. Most of the schematic
capture packages that I have used allow you to draw a stub of a wire to
a component pin and assign it a net name. All stubs that have the same
name are on the same net and connected even though there is no direct
graphics line on the schematic. This is a "connect by name"
feature and is quite useful in complex designs. Things get a little
more complex when you have busses, which are sort of a short hand for a
collection of similar named nets or have a hierarchical schematic. In
high-end programs nets can be assigned various properties in addition to
just a name and are used to guide the PCB layout process. Things like
the maximum number of vias, trace width, trace spacing, layer and
propagation delay are common. With today's high-speed processors
and memory impedance control and trace propagation delay matching are
critical to proper operation. Once the design is in the PCB layout
stage these net properties can be used to guide both manual and
auto-routing of the board, they are also used for post layout design
rule checking.
Once in the PCB layout program each net becomes a copper tract (or
plane) that connects the component pins assigned to that net.
Most schematic packages will let you output a "net list" which is
usually a text file containing a list of nets in the design and the
component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
layout packages will accept a text file net list as input.
In additon to a list of NET's the PCB layout software needs to know what
footprint to use for a particular component. Generally, but not always,
the footprint name is attached as a property to the component symbol
used when drawing the schematic and provided to the PCB program when the
PCB program reads in the schematic.
Craig
--- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
>
> Whats the concept of "nets" in all this pcb creation process?
>
> Randy
>
[Non-text portions of this message have been removed]
Re: [Homebrew_PCBs] NETS
2011-02-19 by Leon Heller
Nets on a schematic are the connections between pins - pins that are
connected together are on the same net. Nets are automatically allocated
names in sequence, $1, $2, etc with the software I use. They can be
renamed to make them more meaningful - Gnd, +5V, CE, etc.
Net connectivity, and the net names, are carried through to the PCB.
Leon
--
Leon Heller
G1HSM
connected together are on the same net. Nets are automatically allocated
names in sequence, $1, $2, etc with the software I use. They can be
renamed to make them more meaningful - Gnd, +5V, CE, etc.
Net connectivity, and the net names, are carried through to the PCB.
Leon
--
Leon Heller
G1HSM
Re: [Homebrew_PCBs] Re: NETS
2011-02-19 by Randy S.
Awesome thanks ..
So if a pin on an IC for example, goes to a cap, and a resistor .. then that
would be one net thats
attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
like that .. and
the only way something else could become a part of that net name or number would
be if it was
connected directly to the traces going to one of those points ?? Is that correct
?
Randy
________________________________
From: designer_craig <cs6061@...>
To: Homebrew_PCBs@yahoogroups.com
Sent: Sat, February 19, 2011 4:44:11 AM
Subject: [Homebrew_PCBs] Re: NETS
Randy,
In any electronic circuit, the pins of the various components that are
connected together are called a net. Generally a net connects two or
more component pins and a circuit or schematic design is a collection of
one or more nets. A schematic is just a graphical way of representing
what component pins must be connected together for the design. The
schematic capture program (editor) will assign a net name to each of the
unique nets in the design. Most programs assign the nets a numeric name
but usually allow the user to change this to something more useful like
"reset" or "clock" etc. Debugging a design is much
easier if all the nets have some functional name. Most of the schematic
capture packages that I have used allow you to draw a stub of a wire to
a component pin and assign it a net name. All stubs that have the same
name are on the same net and connected even though there is no direct
graphics line on the schematic. This is a "connect by name"
feature and is quite useful in complex designs. Things get a little
more complex when you have busses, which are sort of a short hand for a
collection of similar named nets or have a hierarchical schematic. In
high-end programs nets can be assigned various properties in addition to
just a name and are used to guide the PCB layout process. Things like
the maximum number of vias, trace width, trace spacing, layer and
propagation delay are common. With today's high-speed processors
and memory impedance control and trace propagation delay matching are
critical to proper operation. Once the design is in the PCB layout
stage these net properties can be used to guide both manual and
auto-routing of the board, they are also used for post layout design
rule checking.
Once in the PCB layout program each net becomes a copper tract (or
plane) that connects the component pins assigned to that net.
Most schematic packages will let you output a "net list" which is
usually a text file containing a list of nets in the design and the
component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
layout packages will accept a text file net list as input.
In additon to a list of NET's the PCB layout software needs to know what
footprint to use for a particular component. Generally, but not always,
the footprint name is attached as a property to the component symbol
used when drawing the schematic and provided to the PCB program when the
PCB program reads in the schematic.
Craig
So if a pin on an IC for example, goes to a cap, and a resistor .. then that
would be one net thats
attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
like that .. and
the only way something else could become a part of that net name or number would
be if it was
connected directly to the traces going to one of those points ?? Is that correct
?
Randy
________________________________
From: designer_craig <cs6061@...>
To: Homebrew_PCBs@yahoogroups.com
Sent: Sat, February 19, 2011 4:44:11 AM
Subject: [Homebrew_PCBs] Re: NETS
Randy,
In any electronic circuit, the pins of the various components that are
connected together are called a net. Generally a net connects two or
more component pins and a circuit or schematic design is a collection of
one or more nets. A schematic is just a graphical way of representing
what component pins must be connected together for the design. The
schematic capture program (editor) will assign a net name to each of the
unique nets in the design. Most programs assign the nets a numeric name
but usually allow the user to change this to something more useful like
"reset" or "clock" etc. Debugging a design is much
easier if all the nets have some functional name. Most of the schematic
capture packages that I have used allow you to draw a stub of a wire to
a component pin and assign it a net name. All stubs that have the same
name are on the same net and connected even though there is no direct
graphics line on the schematic. This is a "connect by name"
feature and is quite useful in complex designs. Things get a little
more complex when you have busses, which are sort of a short hand for a
collection of similar named nets or have a hierarchical schematic. In
high-end programs nets can be assigned various properties in addition to
just a name and are used to guide the PCB layout process. Things like
the maximum number of vias, trace width, trace spacing, layer and
propagation delay are common. With today's high-speed processors
and memory impedance control and trace propagation delay matching are
critical to proper operation. Once the design is in the PCB layout
stage these net properties can be used to guide both manual and
auto-routing of the board, they are also used for post layout design
rule checking.
Once in the PCB layout program each net becomes a copper tract (or
plane) that connects the component pins assigned to that net.
Most schematic packages will let you output a "net list" which is
usually a text file containing a list of nets in the design and the
component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
layout packages will accept a text file net list as input.
In additon to a list of NET's the PCB layout software needs to know what
footprint to use for a particular component. Generally, but not always,
the footprint name is attached as a property to the component symbol
used when drawing the schematic and provided to the PCB program when the
PCB program reads in the schematic.
Craig
--- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
>
> Whats the concept of "nets" in all this pcb creation process?
>
> Randy
>
[Non-text portions of this message have been removed]
[Non-text portions of this message have been removed]
Re: [Homebrew_PCBs] NETS
2011-02-19 by Jim Tonne
Before schematic entry as we know it today,
all circuit analysis programs used netlists as
the input method. This includes of course
SPICE and all of the other analyzers.
Sure am glad those are bygone days :-)
- JimT
all circuit analysis programs used netlists as
the input method. This includes of course
SPICE and all of the other analyzers.
Sure am glad those are bygone days :-)
- JimT
> Not sure how far back NETS go . . .
Re: [Homebrew_PCBs] NETS
2011-02-19 by Leon Heller
On 19/02/2011 18:52, Jim Tonne wrote:
designing filters:
http://www.tonnesoftware.com/
Leon
--
Leon Heller
G1HSM
>Jim is the author of Elsie, a very useful piece of software for
> Before schematic entry as we know it today,
> all circuit analysis programs used netlists as
> the input method. This includes of course
> SPICE and all of the other analyzers.
designing filters:
http://www.tonnesoftware.com/
Leon
--
Leon Heller
G1HSM
Re: [Homebrew_PCBs] NETS
2011-02-19 by Jim Tonne
I am working on an active bandpass designer
(another freebie) and came up for air and saw
Leon's note.
Leon: Where do I send payment for that? :-)
- JimT
(another freebie) and came up for air and saw
Leon's note.
Leon: Where do I send payment for that? :-)
- JimT
Re: NETS
2011-02-20 by designer_craig
Yes, if you connect a new component pin up to a existing net becomes part of the net. There is an exception in the PCB layout program. It is sometimes possible to run some copper tracts that would allow you to short two different nets. This can happen in a hand rout situation but the post layout design rule checks should flag this.
Sometimes its desirable to connect two nets together, like for example a signal ground net connecting to a chassis ground net. You have component pins on each net but want them connected together only at one point on the layout for signal integrity reasons. So some packages have a virtual component you place on the schematic, it has two pins one connected to each net. No actual component is put on the board it just allows you to connect the two nets without the DRC's complaining that you have shorted the nets.
Craig
Sometimes its desirable to connect two nets together, like for example a signal ground net connecting to a chassis ground net. You have component pins on each net but want them connected together only at one point on the layout for signal integrity reasons. So some packages have a virtual component you place on the schematic, it has two pins one connected to each net. No actual component is put on the board it just allows you to connect the two nets without the DRC's complaining that you have shorted the nets.
Craig
--- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
>
> Awesome thanks ..
> So if a pin on an IC for example, goes to a cap, and a resistor .. then that
> would be one net thats
> attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
> like that .. and
> the only way something else could become a part of that net name or number would
> be if it was
> connected directly to the traces going to one of those points ?? Is that correct
> ?
>
> Randy
>
>
>
>
> ________________________________
> From: designer_craig <cs6061@...>
> To: Homebrew_PCBs@yahoogroups.com
> Sent: Sat, February 19, 2011 4:44:11 AM
> Subject: [Homebrew_PCBs] Re: NETS
>
>
>
> Randy,
>
> In any electronic circuit, the pins of the various components that are
> connected together are called a net. Generally a net connects two or
> more component pins and a circuit or schematic design is a collection of
> one or more nets. A schematic is just a graphical way of representing
> what component pins must be connected together for the design. The
> schematic capture program (editor) will assign a net name to each of the
> unique nets in the design. Most programs assign the nets a numeric name
> but usually allow the user to change this to something more useful like
> "reset" or "clock" etc. Debugging a design is much
> easier if all the nets have some functional name. Most of the schematic
> capture packages that I have used allow you to draw a stub of a wire to
> a component pin and assign it a net name. All stubs that have the same
> name are on the same net and connected even though there is no direct
> graphics line on the schematic. This is a "connect by name"
> feature and is quite useful in complex designs. Things get a little
> more complex when you have busses, which are sort of a short hand for a
> collection of similar named nets or have a hierarchical schematic. In
> high-end programs nets can be assigned various properties in addition to
> just a name and are used to guide the PCB layout process. Things like
> the maximum number of vias, trace width, trace spacing, layer and
> propagation delay are common. With today's high-speed processors
> and memory impedance control and trace propagation delay matching are
> critical to proper operation. Once the design is in the PCB layout
> stage these net properties can be used to guide both manual and
> auto-routing of the board, they are also used for post layout design
> rule checking.
>
> Once in the PCB layout program each net becomes a copper tract (or
> plane) that connects the component pins assigned to that net.
>
> Most schematic packages will let you output a "net list" which is
> usually a text file containing a list of nets in the design and the
> component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
> layout packages will accept a text file net list as input.
>
> In additon to a list of NET's the PCB layout software needs to know what
> footprint to use for a particular component. Generally, but not always,
> the footprint name is attached as a property to the component symbol
> used when drawing the schematic and provided to the PCB program when the
> PCB program reads in the schematic.
>
> Craig
>
> --- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@> wrote:
> >
> > Whats the concept of "nets" in all this pcb creation process?
> >
> > Randy
> >
>
> [Non-text portions of this message have been removed]
>
>
>
>
>
>
>
> [Non-text portions of this message have been removed]
>
Re: [Homebrew_PCBs] Re: NETS
2011-02-20 by Randy S.
Oh ok .. yeah .. makes sense ..
I dont think FreePCB will let you do that ..
One nice thing in it .. is you can create your own parts
in the footprint editor and IF you edit an existing part,
as I did, because I didnt like the pad size for the component,
when you return to the pcb it ask you if you want to replace
the ones existing on the pcb with the new ones .. :)
and in my case with 16 diodes and 12 resistors ..
I said yes to all .. ;)
Randy
________________________________
From: designer_craig <cs6061@...>
To: Homebrew_PCBs@yahoogroups.com
Sent: Sat, February 19, 2011 8:22:02 PM
Subject: [Homebrew_PCBs] Re: NETS
Yes, if you connect a new component pin up to a existing net becomes part of the
net. There is an exception in the PCB layout program. It is sometimes possible
to run some copper tracts that would allow you to short two different nets. This
can happen in a hand rout situation but the post layout design rule checks
should flag this.
Sometimes its desirable to connect two nets together, like for example a signal
ground net connecting to a chassis ground net. You have component pins on each
net but want them connected together only at one point on the layout for signal
integrity reasons. So some packages have a virtual component you place on the
schematic, it has two pins one connected to each net. No actual component is put
on the board it just allows you to connect the two nets without the DRC's
complaining that you have shorted the nets.
Craig
I dont think FreePCB will let you do that ..
One nice thing in it .. is you can create your own parts
in the footprint editor and IF you edit an existing part,
as I did, because I didnt like the pad size for the component,
when you return to the pcb it ask you if you want to replace
the ones existing on the pcb with the new ones .. :)
and in my case with 16 diodes and 12 resistors ..
I said yes to all .. ;)
Randy
________________________________
From: designer_craig <cs6061@...>
To: Homebrew_PCBs@yahoogroups.com
Sent: Sat, February 19, 2011 8:22:02 PM
Subject: [Homebrew_PCBs] Re: NETS
Yes, if you connect a new component pin up to a existing net becomes part of the
net. There is an exception in the PCB layout program. It is sometimes possible
to run some copper tracts that would allow you to short two different nets. This
can happen in a hand rout situation but the post layout design rule checks
should flag this.
Sometimes its desirable to connect two nets together, like for example a signal
ground net connecting to a chassis ground net. You have component pins on each
net but want them connected together only at one point on the layout for signal
integrity reasons. So some packages have a virtual component you place on the
schematic, it has two pins one connected to each net. No actual component is put
on the board it just allows you to connect the two nets without the DRC's
complaining that you have shorted the nets.
Craig
--- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
>
> Awesome thanks ..
> So if a pin on an IC for example, goes to a cap, and a resistor .. then that
> would be one net thats
> attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
> like that .. and
> the only way something else could become a part of that net name or number
>would
>
> be if it was
> connected directly to the traces going to one of those points ?? Is that
>correct
>
> ?
>
> Randy
>
>
>
>
> ________________________________
> From: designer_craig <cs6061@...>
> To: Homebrew_PCBs@yahoogroups.com
> Sent: Sat, February 19, 2011 4:44:11 AM
> Subject: [Homebrew_PCBs] Re: NETS
>
>
>
> Randy,
>
> In any electronic circuit, the pins of the various components that are
> connected together are called a net. Generally a net connects two or
> more component pins and a circuit or schematic design is a collection of
> one or more nets. A schematic is just a graphical way of representing
> what component pins must be connected together for the design. The
> schematic capture program (editor) will assign a net name to each of the
> unique nets in the design. Most programs assign the nets a numeric name
> but usually allow the user to change this to something more useful like
> "reset" or "clock" etc. Debugging a design is much
> easier if all the nets have some functional name. Most of the schematic
> capture packages that I have used allow you to draw a stub of a wire to
> a component pin and assign it a net name. All stubs that have the same
> name are on the same net and connected even though there is no direct
> graphics line on the schematic. This is a "connect by name"
> feature and is quite useful in complex designs. Things get a little
> more complex when you have busses, which are sort of a short hand for a
> collection of similar named nets or have a hierarchical schematic. In
> high-end programs nets can be assigned various properties in addition to
> just a name and are used to guide the PCB layout process. Things like
> the maximum number of vias, trace width, trace spacing, layer and
> propagation delay are common. With today's high-speed processors
> and memory impedance control and trace propagation delay matching are
> critical to proper operation. Once the design is in the PCB layout
> stage these net properties can be used to guide both manual and
> auto-routing of the board, they are also used for post layout design
> rule checking.
>
> Once in the PCB layout program each net becomes a copper tract (or
> plane) that connects the component pins assigned to that net.
>
> Most schematic packages will let you output a "net list" which is
> usually a text file containing a list of nets in the design and the
> component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
> layout packages will accept a text file net list as input.
>
> In additon to a list of NET's the PCB layout software needs to know what
> footprint to use for a particular component. Generally, but not always,
> the footprint name is attached as a property to the component symbol
> used when drawing the schematic and provided to the PCB program when the
> PCB program reads in the schematic.
>
> Craig
>
> --- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@> wrote:
> >
> > Whats the concept of "nets" in all this pcb creation process?
> >
> > Randy
> >
>
> [Non-text portions of this message have been removed]
>
>
>
>
>
>
>
> [Non-text portions of this message have been removed]
>
[Non-text portions of this message have been removed]
Re: [Homebrew_PCBs] Re: NETS
2011-02-20 by Piers Goodhew
.. and there's always the zero Ohm resistor - handy for joining nets. (Handy also for going over traces on 1 (or few) layer(s) boards - except then things that really should be on the same net aren't)
PG
PG
On 20/02/2011, at 12:22 PM, designer_craig wrote:
> Yes, if you connect a new component pin up to a existing net becomes part of the net. There is an exception in the PCB layout program. It is sometimes possible to run some copper tracts that would allow you to short two different nets. This can happen in a hand rout situation but the post layout design rule checks should flag this.
>
> Sometimes its desirable to connect two nets together, like for example a signal ground net connecting to a chassis ground net. You have component pins on each net but want them connected together only at one point on the layout for signal integrity reasons. So some packages have a virtual component you place on the schematic, it has two pins one connected to each net. No actual component is put on the board it just allows you to connect the two nets without the DRC's complaining that you have shorted the nets.
>
> Craig
>
> --- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
> >
> > Awesome thanks ..
> > So if a pin on an IC for example, goes to a cap, and a resistor .. then that
> > would be one net thats
> > attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
> > like that .. and
> > the only way something else could become a part of that net name or number would
> > be if it was
> > connected directly to the traces going to one of those points ?? Is that correct
> > ?
> >
> > Randy
> >
> >
> >
> >
> > ________________________________
> > From: designer_craig <cs6061@...>
> > To: Homebrew_PCBs@yahoogroups.com
> > Sent: Sat, February 19, 2011 4:44:11 AM
> > Subject: [Homebrew_PCBs] Re: NETS
> >
> >
> >
> > Randy,
> >
> > In any electronic circuit, the pins of the various components that are
> > connected together are called a net. Generally a net connects two or
> > more component pins and a circuit or schematic design is a collection of
> > one or more nets. A schematic is just a graphical way of representing
> > what component pins must be connected together for the design. The
> > schematic capture program (editor) will assign a net name to each of the
> > unique nets in the design. Most programs assign the nets a numeric name
> > but usually allow the user to change this to something more useful like
> > "reset" or "clock" etc. Debugging a design is much
> > easier if all the nets have some functional name. Most of the schematic
> > capture packages that I have used allow you to draw a stub of a wire to
> > a component pin and assign it a net name. All stubs that have the same
> > name are on the same net and connected even though there is no direct
> > graphics line on the schematic. This is a "connect by name"
> > feature and is quite useful in complex designs. Things get a little
> > more complex when you have busses, which are sort of a short hand for a
> > collection of similar named nets or have a hierarchical schematic. In
> > high-end programs nets can be assigned various properties in addition to
> > just a name and are used to guide the PCB layout process. Things like
> > the maximum number of vias, trace width, trace spacing, layer and
> > propagation delay are common. With today's high-speed processors
> > and memory impedance control and trace propagation delay matching are
> > critical to proper operation. Once the design is in the PCB layout
> > stage these net properties can be used to guide both manual and
> > auto-routing of the board, they are also used for post layout design
> > rule checking.
> >
> > Once in the PCB layout program each net becomes a copper tract (or
> > plane) that connects the component pins assigned to that net.
> >
> > Most schematic packages will let you output a "net list" which is
> > usually a text file containing a list of nets in the design and the
> > component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
> > layout packages will accept a text file net list as input.
> >
> > In additon to a list of NET's the PCB layout software needs to know what
> > footprint to use for a particular component. Generally, but not always,
> > the footprint name is attached as a property to the component symbol
> > used when drawing the schematic and provided to the PCB program when the
> > PCB program reads in the schematic.
> >
> > Craig
> >
> > --- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@> wrote:
> > >
> > > Whats the concept of "nets" in all this pcb creation process?
> > >
> > > Randy
> > >
> >
> > [Non-text portions of this message have been removed]
> >
> >
> >
> >
> >
> >
> >
> > [Non-text portions of this message have been removed]
> >
>
>
Re: [Homebrew_PCBs] Re: NETS
2011-02-20 by Andrew Hakman
On Sat, Feb 19, 2011 at 6:22 PM, designer_craig <cs6061@...> wrote:
those pesky "wire patches" that connect 2 nets together - no component gets
placed in the design either, and they lead to all kinds of interesting fun
if you skip some automated check steps (because the tech kit doesn't work
properly with the verification tools, and there's no time to fix it before
the deadline), like completely dead ASICs - OOPS! The project I'm working on
has had at least 3 completely DOA ASIC runs, due to issues around connecting
different nets together! Good thing it's just grad school - in the real
world, I'm sure people would've been fired! Probably especially in the 2
cases where VDD got inadvertantly connected to GND - yay, we built a $5000
heater!
Andrew
[Non-text portions of this message have been removed]
>Heh, and if you're a *HDL designer / ASIC person, you got to watch out for
>
> Yes, if you connect a new component pin up to a existing net becomes part
> of the net. There is an exception in the PCB layout program. It is sometimes
> possible to run some copper tracts that would allow you to short two
> different nets. This can happen in a hand rout situation but the post layout
> design rule checks should flag this.
>
> Sometimes its desirable to connect two nets together, like for example a
> signal ground net connecting to a chassis ground net. You have component
> pins on each net but want them connected together only at one point on the
> layout for signal integrity reasons. So some packages have a virtual
> component you place on the schematic, it has two pins one connected to each
> net. No actual component is put on the board it just allows you to connect
> the two nets without the DRC's complaining that you have shorted the nets.
>
those pesky "wire patches" that connect 2 nets together - no component gets
placed in the design either, and they lead to all kinds of interesting fun
if you skip some automated check steps (because the tech kit doesn't work
properly with the verification tools, and there's no time to fix it before
the deadline), like completely dead ASICs - OOPS! The project I'm working on
has had at least 3 completely DOA ASIC runs, due to issues around connecting
different nets together! Good thing it's just grad school - in the real
world, I'm sure people would've been fired! Probably especially in the 2
cases where VDD got inadvertantly connected to GND - yay, we built a $5000
heater!
Andrew
[Non-text portions of this message have been removed]
Re: [Homebrew_PCBs] Re: NETS
2011-02-20 by Donald H Locker
It happens in the "real" world too, I'm afraid.
Donald.
--
*Plain Text* email -- it's an accessibility issue
() no proprietary attachments; no html mail
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Donald.
--
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----- Original Message -----
> From: "Andrew Hakman" <andrew.hakman@...>
> To: "Homebrew PCBs" <Homebrew_PCBs@yahoogroups.com>
> Cc: "designer_craig" <cs6061@...>
> Sent: Sunday, February 20, 2011 1:56:45 AM
> Subject: Re: [Homebrew_PCBs] Re: NETS
>
> On Sat, Feb 19, 2011 at 6:22 PM, designer_craig <cs6061@...>
> wrote:
>
> >
> >
> > Yes, if you connect a new component pin up to a existing net becomes
> part
> > of the net. There is an exception in the PCB layout program. It is
> sometimes
> > possible to run some copper tracts that would allow you to short
> two
> > different nets. This can happen in a hand rout situation but the
> post layout
> > design rule checks should flag this.
> >
> > Sometimes its desirable to connect two nets together, like for
> example a
> > signal ground net connecting to a chassis ground net. You have
> component
> > pins on each net but want them connected together only at one point
> on the
> > layout for signal integrity reasons. So some packages have a
> virtual
> > component you place on the schematic, it has two pins one connected
> to each
> > net. No actual component is put on the board it just allows you to
> connect
> > the two nets without the DRC's complaining that you have shorted the
> nets.
> >
>
> Heh, and if you're a *HDL designer / ASIC person, you got to watch out
> for
> those pesky "wire patches" that connect 2 nets together - no component
> gets
> placed in the design either, and they lead to all kinds of interesting
> fun
> if you skip some automated check steps (because the tech kit doesn't
> work
> properly with the verification tools, and there's no time to fix it
> before
> the deadline), like completely dead ASICs - OOPS! The project I'm
> working on
> has had at least 3 completely DOA ASIC runs, due to issues around
> connecting
> different nets together! Good thing it's just grad school - in the
> real
> world, I'm sure people would've been fired! Probably especially in the
> 2
> cases where VDD got inadvertantly connected to GND - yay, we built a
> $5000
> heater!
>
> Andrew
>
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Be sure to visit the group home and check for new Links, Files, and
> Photos:
> http://groups.yahoo.com/group/Homebrew_PCBsYahoo! Groups Links
>
>
>
Re: [Homebrew_PCBs] Re: NETS
2011-02-21 by Bob Butcher
Hi Randy,
You are close to being correct here. A picture may help make this more understandable. Attached are three files, named netlist, schematic, and Power Port, which you should open to make this more understandable.
Three exceptions I can think for connecting nets, besides a wire, are related to your layout software. I use Protel and it allows naming nets by placing a label on the net. If two nets are both labeled the same, then they will be connected. Another case is if I use a port, and place an identical port on other nets, they will be connected. A third case is a symbol, often the ground symbol, however others are allowed. A net name is associated with the symbol, and all nets with the same symbol and same name are connected. On the schematic, there are 10 resistors, all 1K value, named R1 through R10. Each resistor has two leads, numbered 1 or 2 (i.e. R3-1 and R3-2) to keep every connection unique. If we had a 16 pin IC named U1, then the pins would be numbered U1-1 through U1-16. All the lower ends of the resistors (Pin 1 in this case) are connected to the GND net. R1 through R6 are connected using the Power Ground symbol. R7 & R8 are connected to the GND
net using a net label. R9 & R10 are connected to the GND net using a PORT, which was named GND. Protel uses a similar method for naming components, ports, and symbols as shown in the figure called Power Port.jpg. The name GND is associated with the Power Ground Symbol, and a similar method was used for naming all 10 resistors, the other PORTs (named VCC) and the net label. Note that the top end of R5, R6, R9, & R10 are all connected to net VCC by a PORT. The top ends of R1 & R2 are connected to each other, but no name was used, so Protel will assign a name for this net, as will be done with the top ends of R3 & R4, and R7 & R8.
If you look at the figure netlist.jpg, the top portion defines the components, R1 through R10 and provides a value for each component. In some cases other information usually will be included in the component definitions, including a footprint that would be used by the PCB layout software. I did not include a footprint when I drew the schematic, so this netlist would not be very useful in the PCB layout, and in fact would generate a missing footprint error.
The bottom portion of the netlist shows the net names that were either named on the schematic (GND), or named by Protel (NetR1_2, NetR3_2, NetR5_2, and NetR9_1). Note that although we named a net VCC with a PORT, Protel did not use that name, instead it used a name of NetR5-2. If we had used a net label instead of a PORT, the net label name would have been used in the netlist. This may vary between different schematic capture programs, but the important point is that all the components connected to each other, however it is done, have the same unique net name.
I did not show an example here, but if you include a footprint in your component identification on the schematic, then you can open the netlist using your PCB layout software and it will place the footprint on the PCB. For example I could have assigned a 1206 footprint (surface mount) to the resistors, and the PCB layout software would search my footprint library for a 1206 footprint, and if found, would place a copy of it for each resistor using that footprint. I could have assigned a custom footprint that I created to some of the resistors, so some could be through hole resistors, or perhaps an 805 surface mount footprint (smaller than a 1206). The PCB layout program will also create a "spider web" of lines connecting the nets which assist in manually placing traces between pads that should be connected. A set of design rules can be created that will specify the spacing between traces, trace sizes for each net, and many other features too numerous to
list here. PCB layout is another topic so I will not discuss it further here.
Bob Butcher
[Non-text portions of this message have been removed]
You are close to being correct here. A picture may help make this more understandable. Attached are three files, named netlist, schematic, and Power Port, which you should open to make this more understandable.
Three exceptions I can think for connecting nets, besides a wire, are related to your layout software. I use Protel and it allows naming nets by placing a label on the net. If two nets are both labeled the same, then they will be connected. Another case is if I use a port, and place an identical port on other nets, they will be connected. A third case is a symbol, often the ground symbol, however others are allowed. A net name is associated with the symbol, and all nets with the same symbol and same name are connected. On the schematic, there are 10 resistors, all 1K value, named R1 through R10. Each resistor has two leads, numbered 1 or 2 (i.e. R3-1 and R3-2) to keep every connection unique. If we had a 16 pin IC named U1, then the pins would be numbered U1-1 through U1-16. All the lower ends of the resistors (Pin 1 in this case) are connected to the GND net. R1 through R6 are connected using the Power Ground symbol. R7 & R8 are connected to the GND
net using a net label. R9 & R10 are connected to the GND net using a PORT, which was named GND. Protel uses a similar method for naming components, ports, and symbols as shown in the figure called Power Port.jpg. The name GND is associated with the Power Ground Symbol, and a similar method was used for naming all 10 resistors, the other PORTs (named VCC) and the net label. Note that the top end of R5, R6, R9, & R10 are all connected to net VCC by a PORT. The top ends of R1 & R2 are connected to each other, but no name was used, so Protel will assign a name for this net, as will be done with the top ends of R3 & R4, and R7 & R8.
If you look at the figure netlist.jpg, the top portion defines the components, R1 through R10 and provides a value for each component. In some cases other information usually will be included in the component definitions, including a footprint that would be used by the PCB layout software. I did not include a footprint when I drew the schematic, so this netlist would not be very useful in the PCB layout, and in fact would generate a missing footprint error.
The bottom portion of the netlist shows the net names that were either named on the schematic (GND), or named by Protel (NetR1_2, NetR3_2, NetR5_2, and NetR9_1). Note that although we named a net VCC with a PORT, Protel did not use that name, instead it used a name of NetR5-2. If we had used a net label instead of a PORT, the net label name would have been used in the netlist. This may vary between different schematic capture programs, but the important point is that all the components connected to each other, however it is done, have the same unique net name.
I did not show an example here, but if you include a footprint in your component identification on the schematic, then you can open the netlist using your PCB layout software and it will place the footprint on the PCB. For example I could have assigned a 1206 footprint (surface mount) to the resistors, and the PCB layout software would search my footprint library for a 1206 footprint, and if found, would place a copy of it for each resistor using that footprint. I could have assigned a custom footprint that I created to some of the resistors, so some could be through hole resistors, or perhaps an 805 surface mount footprint (smaller than a 1206). The PCB layout program will also create a "spider web" of lines connecting the nets which assist in manually placing traces between pads that should be connected. A set of design rules can be created that will specify the spacing between traces, trace sizes for each net, and many other features too numerous to
list here. PCB layout is another topic so I will not discuss it further here.
Bob Butcher
[Non-text portions of this message have been removed]