Doepfer

Hi Florian,

> This approach has the disadvantage that the voltage always will drop 
> between two triggers. It will be like a sawtooth waveform; the lower the 
> trigger rate is the more the voltage will look like a sawtooth. And the 
> higher a change of rate is, the worse the slewlimiter will represent the 
> change of rates. 

That's correct. One has to find a compromise between slew time and ripple of the output voltage.

> I think the counter based approach is more exact and it 
> would not be that difficult to implement: simple CD4069 based clock 
> oscillator, two stacked 4bit downcounters (4526) to create the 8bit 
> value, and a resistor ladder D/A converter using buffers from the same 
> 4069 as the clock oscillator, a TL062 as buffer, some resistors/caps around.

I agree. But this requires a lot of DIY experience. The version with A-162 and A-170 could be realized with existing modules.

Best wishes
Dieter