AVR-Chat

I solved some hardware problems and now the ADC is
more stable.  This is the source code:

void init_adc(void)
{
	ADMUX |= (0x01 << 6);
	ADMUX &= (~ (0x01 << 7));
	ADCSRA = 0xE0;
	DDRA = 0x00;
}

unsigned int read_adc(void)
{
	int adc;
	adc = (ADCW & 0x03FF);
	return adc;
}

I tried to improve the accuracy by lowering the adc
clock:
	ADCSRA = 0xE0 | 0x07;//set last 3 bits
that was to set bits ADPS2, ADPS1, ADPS0.  Doing that
the prescaler is set to use a division factor of 128. 
But it doesn't make the ADC more stable.  Actually, it
makes it less accurate, do you know why?

Jose




 --- Dave VanHorn <dvanhorn@dvanhorn.org> escribió: 
> 
> 
> >
> >I get a rock steady ADC reading using AVR chips
> with 2 resistors on the input.
> >That is without sleep mode or an LC filter. That is
> using a 115.2KHz ADC 
> >clock.
> >Anything lower than 200KHz should be fine.
> 
> Indeed.
> 
> There are constraints to be observed, like when you
> change channels, and 
> making sure that your Vref is quiet.
> 
> You should filter the input though, no sense having
> anything on the input 
> that is significantly faster than your sample rate,
> or even any where near 
> your sample rate.
> I get a couple of bits dither, but the systems that
> I'm working in aren't 
> really designed for low noise, nor do they care. 
> The upper 8 bits is 
> plenty, so I didn't bother cleaning up the stuff
> that's below the noise floor.
> 
> 
> 
> 
>  
> Yahoo! Groups Links
> 
> 
>     AVR-Chat-unsubscribe@yahoogroups.com
> 
>  
> 
> 
> 
>  


		
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