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Memory Access Time

Memory Access Time

2004-06-24 by Ivo Strebel

Hello All,

Do I have a problem?

Hardware:
CPU:    68332GCPV25 (it runs at 25MHz)
RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
Register:
DSACK:  0
Used-Signals:
Databus:    D0-15
Adressbus:  A1-A18
CS: CS0  (low byte)
    CS1  (high byte)

My system is running great, but there is following insecurity:

WS = 0
tcyc=39.7ns
Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)-tdicl(min)
Chip-select access time (MCU Read cycle) =  55.4ns

I measured the signal CS0/CS1 several time and the width seems to be stable at
80 ns (2*tcyc). According to which circumstances will the CS signal be  55.4ns?
Will it ever be? Do I really have to add a wait-state  (I am reliant on the speed).
If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
Which SRAM do you guys use at 25 MHz.

Thx Ivo Strebel

Re: [68300] Memory Access Time

2004-06-24 by jeffrey.tenney@gm.com

Ivo,

Yes, you have a problem.  You'll need one wait state (not zero) to use 70ns
memory with a 25MHz '332.

As your tool tells you, zero wait states require 55ns memory or faster.

Fast-Termination mode requires 15ns memory or faster.

For our 25MHz 683xx designs, we use Alliance parts
(http://www.alsc.com/products/fastasync.htm).  We always choose a 15nS part
so we can use Fast-Termination cycles.  Their stuff works great.

Jeff



|---------+---------------------------->
|         |           "Ivo Strebel"    |
|         |           <Ivo.Strebel@schi|
|         |           ller.ch>         |
|         |                            |
|         |           06/24/2004 07:47 |
|         |           AM               |
|         |           Please respond to|
|         |           68300            |
|         |                            |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       <68300@yahoogroups.com>                                                                                      |
  |       cc:                                                                                                                    |
  |       Subject:  [68300] Memory Access Time                                                                                   |
  >------------------------------------------------------------------------------------------------------------------------------|




Hello All,

Do I have a problem?

Hardware:
CPU:    68332GCPV25 (it runs at 25MHz)
RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
Register:
DSACK:  0
Used-Signals:
Databus:    D0-15
Adressbus:  A1-A18
CS: CS0  (low byte)
    CS1  (high byte)

My system is running great, but there is following insecurity:

WS = 0
tcyc=39.7ns
Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)
-tdicl(min)
Chip-select access time (MCU Read cycle) =  55.4ns

I measured the signal CS0/CS1 several time and the width seems to be stable
at
80 ns (2*tcyc). According to which circumstances will the CS signal be
55.4ns?
Will it ever be? Do I really have to add a wait-state  (I am reliant on the
speed).
If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
Which SRAM do you guys use at 25 MHz.

Thx Ivo Strebel




---------------------------------------------------To learn more about
Motorola Microcontrollers, please visit
http://www.motorola.com/mcu

learn more about Motorola Microcontrollers, please visit
http://www.motorola.com/mcu


Yahoo! Groups Links

Re: Re: [68300] Memory Access Time

2004-06-25 by liubo

jeffrey.tenney,\ufffd\ufffd\ufffd�\ufffd
 	Charles once said to me:
	Question: I use 68332 at 25M clk,do I need to select a high speed memory chip?Is it enough
if I use 70ns speed chip? 
    Answer: I believe that the minimum access time is two full S-clock cycles.  The S-clock is 
essentially equal to the internal bus speed.  I have not gone through the calculations but I 
believe that you actually need 80 ns. memory to run with no wait states at 25 MHZ  (40 ns period).  
Anyway, 70 ns would do.

	I use 70ns memory chip in my system(DSACK set to internal,no wait state)it works ok.But I don't 
use the fast termination mode.

	

======= 2004-06-24 09:38:00 \ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u0434\ufffd\ufffd\ufffd\ufffd=======

>Ivo,
>
>Yes, you have a problem.  You'll need one wait state (not zero) to use 70ns
>memory with a 25MHz '332.
>
>As your tool tells you, zero wait states require 55ns memory or faster.
>
>Fast-Termination mode requires 15ns memory or faster.
>
>For our 25MHz 683xx designs, we use Alliance parts
>(http://www.alsc.com/products/fastasync.htm).  We always choose a 15nS part
>so we can use Fast-Termination cycles.  Their stuff works great.
>
>Jeff
>
>
>
>|---------+---------------------------->
>|         |           "Ivo Strebel"    |
>|         |           <Ivo.Strebel@schi|
>|         |           ller.ch>         |
>|         |                            |
>|         |           06/24/2004 07:47 |
>|         |           AM               |
>|         |           Please respond to|
>|         |           68300            |
>|         |                            |
>|---------+---------------------------->
>  >------------------------------------------------------------------------------------------------------------------------------|
>  |                                                                                                                              |
>  |       To:       <68300@yahoogroups.com>                                                                                      |
>  |       cc:                                                                                                                    |
>  |       Subject:  [68300] Memory Access Time                                                                                   |
>  >------------------------------------------------------------------------------------------------------------------------------|
>
>
>
>
>Hello All,
>
>Do I have a problem?
>
>Hardware:
>CPU:    68332GCPV25 (it runs at 25MHz)
>RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
>Register:
>DSACK:  0
>Used-Signals:
>Databus:    D0-15
>Adressbus:  A1-A18
>CS: CS0  (low byte)
>    CS1  (high byte)
>
>My system is running great, but there is following insecurity:
>
>WS = 0
>tcyc=39.7ns
>Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)
>-tdicl(min)
>Chip-select access time (MCU Read cycle) =  55.4ns
>
>I measured the signal CS0/CS1 several time and the width seems to be stable
>at
>80 ns (2*tcyc). According to which circumstances will the CS signal be
>55.4ns?
>Will it ever be? Do I really have to add a wait-state  (I am reliant on the
>speed).
>If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
>Which SRAM do you guys use at 25 MHz.
>
>Thx Ivo Strebel
>
>
>
>
>---------------------------------------------------To learn more about
>Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
>
>
>
>---------------------------------------------------To learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
> 
>Yahoo! Groups Links
>
>
>
> 

= = = = = = = = = = = = = = = = = = = =
			

\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd
\ufffd\ufffd
 
				 
\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffdliubo
\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffdboliu@...
\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd2004-06-25

Re: Re: [68300] Memory Access Time

2004-06-25 by jeffrey.tenney@gm.com

Liubo, Ivo,

At 25.17 MHz and zero wait states, your bus cycle has S1, S2, S3, and S4
which total 79.5ns.

In the worst case, the '332 asserts CS* 19ns after the start of S1.  The
RAM must provide valid data by 5ns prior to the end of S4.

79.5 - 19 - 5 = 55.5

So your RAM must be able to produce data reliably 55ns after the '332
asserts CS* for a zero-wait-state READ.

Your 70ns chips are working because both the analysis above and the 70ns
timing rating consider the worst cases, both of which are nicely
guardbanded.  However, that approach is technically out of spec.

Jeff



|---------+---------------------------->
|         |           "liubo"          |
|         |           <boliu@263.net>  |
|         |                            |
|         |           06/24/2004 06:49 |
|         |           PM               |
|         |           Please respond to|
|         |           68300            |
|         |                            |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       "68300@yahoogroups.com" <68300@yahoogroups.com>                                                              |
  |       cc:                                                                                                                    |
  |       Subject:  Re: Re: [68300] Memory Access Time                                                                           |
  >------------------------------------------------------------------------------------------------------------------------------|




jeffrey.tenney,您好!
             Charles once said to me:
             Question: I use 68332 at 25M clk,do I need to select a high
speed memory chip?Is it enough
if I use 70ns speed chip?
    Answer: I believe that the minimum access time is two full S-clock
cycles.  The S-clock is
essentially equal to the internal bus speed.  I have not gone through the
calculations but I
believe that you actually need 80 ns. memory to run with no wait states at
25 MHZ  (40 ns period).
Anyway, 70 ns would do.

             I use 70ns memory chip in my system(DSACK set to internal,no
wait state)it works ok.But I don't
use the fast termination mode.



======= 2004-06-24 09:38:00 您在来信中写道:=======

>Ivo,
>
>Yes, you have a problem.  You'll need one wait state (not zero) to use
70ns
>memory with a 25MHz '332.
>
>As your tool tells you, zero wait states require 55ns memory or faster.
>
>Fast-Termination mode requires 15ns memory or faster.
>
>For our 25MHz 683xx designs, we use Alliance parts
>(http://www.alsc.com/products/fastasync.htm).  We always choose a 15nS
part
>so we can use Fast-Termination cycles.  Their stuff works great.
>
>Jeff
>
>
>
>|---------+---------------------------->
>|         |           "Ivo Strebel"    |
>|         |           <Ivo.Strebel@schi|
>|         |           ller.ch>         |
>|         |                            |
>|         |           06/24/2004 07:47 |
>|         |           AM               |
>|         |           Please respond to|
>|         |           68300            |
>|         |                            |
>|---------+---------------------------->
>  >
-------------------------------------------------------------------------------------------------------------------------------|

>  |
|
>  |       To:       <68300@yahoogroups.com>
|
>  |       cc:
|
>  |       Subject:  [68300] Memory Access Time
|
>  >
-------------------------------------------------------------------------------------------------------------------------------|

>
>
>
>
>Hello All,
>
>Do I have a problem?
>
>Hardware:
>CPU:    68332GCPV25 (it runs at 25MHz)
>RAM:    2 * BS62LV2000 (Chip-select access time = (must be)70ns)
>Register:
>DSACK:  0
>Used-Signals:
>Databus:    D0-15
>Adressbus:  A1-A18
>CS: CS0  (low byte)
>    CS1  (high byte)
>
>My system is running great, but there is following insecurity:
>
>WS = 0
>tcyc=39.7ns
>Chip-select access time (MCU Read cycle) = (2+WS) * tcyc * tclsa(max)
>-tdicl(min)
>Chip-select access time (MCU Read cycle) =  55.4ns
>
>I measured the signal CS0/CS1 several time and the width seems to be
stable
>at
>80 ns (2*tcyc). According to which circumstances will the CS signal be
>55.4ns?
>Will it ever be? Do I really have to add a wait-state  (I am reliant on
the
>speed).
>If the CS0/CS1 drops down under 70ns, I would run in to deep problems.
>Which SRAM do you guys use at 25 MHz.
>
>Thx Ivo Strebel
>
>
>
>
>---------------------------------------------------To learn more about
>Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
>
>
>
>---------------------------------------------------To learn more about
Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>
>
>Yahoo! Groups Links
>
>
>
>

= = = = = = = = = = = = = = = = = = = =


        致
礼!


        liubo
        boliu@263.net
          2004-06-25





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---------------------------------------------------To learn more about
Motorola Microcontrollers, please visit
http://www.motorola.com/mcu

learn more about Motorola Microcontrollers, please visit
http://www.motorola.com/mcu


Yahoo! Groups Links

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