[sdiy] Cyclone SID

[Rainer Buchty]

>My plan was to make oscillators + envelopes only, each with their own
>multiplying DAC using SPI interfaces. Any filtering would take place
>after DAC'ing the oscillator. I'll probably thow in a bunch of LFO's
>and a patching matrix as well.

I'd go for for a time-sliced variant, i.e. something like this (C-like):

for(i=0;i<NUM_OSC;i++)
{
	phase=mem_phase[i]+mem_inc[i];
	env=mem_env[i]+mem_env_delta[i];
	
	compute_env(...);

	*channel_port=i;
	*wave_port=phase;
	*env_port=env;

	mem_env[i]=env;
	mem_phase[i]=phase;
}

That way you get the maximum out of your FPGA and externally only need a 
DAC, a multiplying DAC, plus some 4051s (or similar).

Rainer