[sdiy] Xilinx 3E board comments

[Magnus Danielson]

From: Harry Bissell Jr <harrybissell at prodigy.net>
Subject: Re: [sdiy] Xilinx 3E board comments
Date: Tue, 13 Jun 2006 17:03:53 -0700 (PDT)
Message-ID: <20060614000353.76997.qmail at web51014.mail.yahoo.com>

> You cannot for example... bring a signal in from the
> outside world and clock something with it directly...
> even if you run it through appropriate buffers etc. 
> 
> This would work with any real-world IC chip...
> 
> You'd need to bring it in as data, clock it with the
> system clock, and then deal with it, Best if you NEVER
> try to use that signal as a clock... but always as
> data.
> 
> Thank God there was someone in our company who was
> able to clue me on that or I'd still be at the
> workbench !!!

Well, it is partly true. But even if it is possible it should really be
avoided. There is a whole bunch of stuff happening and you need to take due
care. I say this with experience since I just happend to have made such a
design and it synthesize neatly and it ticks and ticks and works correctly.
Not big magic, but some minor magic done with some care.

However, whenever you have more than one clock in the system, you must start
to think carefully. Whenever you go with a signal between those clock domains
they need due care. Stuff like re-sampling, buffers etc. needs to be tought
off. If done with care, designs with over 20 clock domains can work as
intended, but you don't see that many in FPGAs thought.

There is a whole bunch of different scales of problems from fully asynchronous
down to fully synchronous. There is different things to consider and different
ways to tacle them. A very common misstake is assuming a better situation than
real life supplies and the logic just won't cut the problem into a solution.
By overdoing it the other way it will be overly complex and then usually hard
to overlook and problems occur due to that.

All these hurdles is part of a learning process. Some can be avoided in the
beginning by some simple rules and some will not make sense at the beginning.
But it is better to work in a "safe" but overly restricted design ruleset to
start off with than having to face all problems before one can (barely) walk.

Cheers,
Magnus