[sdiy] Xilinx 3E board comments

[Eric Brombaugh]

Harry Bissell Jr wrote:
> You cannot for example... bring a signal in from the
> outside world and clock something with it directly...
> even if you run it through appropriate buffers etc. 
>   
True if you're talking about bringing in lots of single signals and 
trying to use them to drive the clock inputs on flops. That's not to say 
you can't have multiple asynchronous clock domains on an FPGA though - 
you can have blocks of logic running from different clocks. You just 
have to be careful about how you cross the boundaries between these 
different clock domains.

Re: Asynchronous design - In the 4000 series they used to have an 
app-note on implementing the tried & true sequential phase/frequency 
detector. Anyone who's ever looked at the guts of one of those knows 
what a tricky mess of asynchronous feedback loops that can be. I 
actually implemented this once and it worked quite nicely for a clean 
PLL. I'm not sure if they still allow this though.

Eric