[sdiy] Xilinx 3E board comments

[Magnus Danielson]

From: Harry Bissell Jr <harrybissell at prodigy.net>
Subject: Re: [sdiy] Xilinx 3E board comments
Date: Tue, 13 Jun 2006 12:53:57 -0700 (PDT)
Message-ID: <20060613195357.67017.qmail at web51004.mail.yahoo.com>

> Oh yes yes yes... do not EVER try
> an asynchronous design in an FPGA you will
> be SO sorry.   Analog dirty-tricks do not
> work.

The asynchronous design-tricks are definitly out, but you may still do some
asynchronous designs, but care needs to be taken. You really want to define
your clock domains and clearly identify signals as belonging to this or that
clockdomain or be one of those obscure "asynchronous signals" from the evil
world outside of the relatively safe world in the FPGA.

To some degree one has to unlearn and to some degree one has to learn how to
properly do things. When you learn just how much hazzle asynchronous brings,
you learn to create bigger and bigger synchronous clock-domains, lock things
together and stuff like that. The beating between two clocks which "almost" has
the same frequency can be annoying as hell and being able to make a fully
covering simulation worth waiting for is somewhat a lucid dream only.

One thing which I've found that people fear is to frequency lock oscillators.
It is "hard", "difficult" and "unstable". IMHO it is usually fairly easy to
acheive and the benefit is a fixed frequency ratio with stable phase-relation-
ship which actually makes minor wonders since it now becomes a synchronous
frequency-relation shift which is very predictable and highly verifiable.
Ah well.

Cheers,
Magnus