[sdiy] Single chip digital delay

[Seb Francis]

Hi Antti,

Antti Huovilainen wrote:

> On Thu, 26 Jan 2006, Seb Francis wrote:
>
>> BBD.  In which case, it will not be good enough for me.  For my 
>> purposes I definitely need a clean (get out what you put in) delay of 
>> 5 to 50ms.  CD (44.1kHz/16bit) is the kind of quality level I'm 
>> aiming for.
>
>
> Seems to me that you need a ADC/DAC or a CODEC + interface + a bit of 
> sram.
>
>> But I still do want a simple (minimum component count) solution...
>
>
> Is three ICs good enough?

Yeah, it's looking like it will have to be..

>
>> My current thinking is to use a high end PIC with some kind of ADC 
>> and DAC on the front and back of it.  Yes I know a DSP chip would be 
>> better, but I have a PIC programmer and I know how to program PICs.  
>> As for the ADC and DAC, I
>
>
> What I'd do is find a suitable oversampling codec (there are many that 
> are cheap and decent quality) and use dsPIC to interface between that 
> (dsPIC has codec interface that can handle the serial datastream) and 
> a cheap 32kbyte SRAM.
>
Do you mean by CODEC, a combined ADC and DAC?  I hadn't even thought 
about looking for such a thing, but it makes sense to use one.

> The caveat: pretty much all modern (read obtainable) codecs, adcs and 
> dacs are SMD.
>
The problem with using a dsPIC is I have only a Picstart Plus which 
can't program them.  But I think a PIC18FXXX would be enough for my 
simple delay application.  As you say though it's tricky to find stuff 
that isn't SMD.  I think I've found some suitable chips though ...

AD677 - 16-Bit, Serial, 100 kSPS Sampling ADC
AD1851 or AD1856 - 16-Bit PCM Audio DACs
Cypress CY62256 - 32kbyte SRAM

Both have SPI interface so it would be easy to interface them with a 
PIC, but I'm a bit confused about the amount of oversampling needed for 
the DAC.  These DACs support up to 16x or 8x oversampling respectively.  
Does this mean they can effectively be driven up to 16x 48kHz?  There 
doesn't seem to be a specific sampling rate figure mentioned on the 
datasheets, although if you do the maths based on the SPI max clock rate 
it looks like they mean 16x 48kHz.  Where am I going to get all this 
data from?  The max data I will have from the ADC will be at 96kHz, and 
even then I'd prefer only to store half of it (48kHz).  How is this 
oversampling data generated?

Seb