[sdiy] PCB layout rules

[John Luciani]

On 12/23/06, Antti Huovilainen <ajhuovil at cc.hut.fi> wrote:
> On Fri, 22 Dec 2006, Joe Grisso wrote:
>
> > I think at sdiy frequencies meaning anything below 25MHz. Layout
> > hardly comes into play below these frequencies, at least the kind of
> > layout work I'm used to now.
>
> Isn't ground bounce a function of switching speed, not switching
> frequency? Modern CPLDs etc seem to have switching times of a few
> nanoseconds, even if you run the design at just 10 MHz. What if you have a
> dozen 128 cell CPLDs in your design (clocked at 10 MHz for example)?

The edge speed is what determines the system frequency. I should have
been more specific. Use the lowest edge speed you can tolerate.
You need to determine how high the switching current is and the impedance
of the planes.

> I think the future of SDIY is in mixed signal designs and there you have
> both fast switching (say 5ns edge time) and low level signals (volt or two
> p-p for an audio dac for example).

If you are going to require large high frequency switching currents and
uV accuracy you will probably need to split the planes. Most of the current
sdiy stuff I have seen seems to be higher signal levels and lower edge speeds.

You could be right about the future of sdiy. Maybe it's time to give
"High-Speed Digital Design" by Johnson and Graham another read ;-)

(* jcl *)

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