[sdiy] PCB layout rules

[Antti Huovilainen]

On Fri, 22 Dec 2006, Joe Grisso wrote:

> I think at sdiy frequencies meaning anything below 25MHz. Layout
> hardly comes into play below these frequencies, at least the kind of
> layout work I'm used to now.

Isn't ground bounce a function of switching speed, not switching 
frequency? Modern CPLDs etc seem to have switching times of a few 
nanoseconds, even if you run the design at just 10 MHz. What if you have a 
dozen 128 cell CPLDs in your design (clocked at 10 MHz for example)?

I think the future of SDIY is in mixed signal designs and there you have 
both fast switching (say 5ns edge time) and low level signals (volt or two 
p-p for an audio dac for example).

Antti

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