[sdiy] PCB layout rules

[Joe Grisso]

On 12/22/06, Paul Perry <pfperry at melbpc.org.au> wrote:
> Here's a problem though.... what do we mean by "sdiy frequencies"?
> Edges of clocks, spikes as oscillators turn over, microprocessors....
> there's a lot happening in most sdiy that involves high speed transitions.
> To say nothing of crap like LEDs that have to be kept separate.
> You can't sweep it under the carpet unless you have a REALLY DEEP
> carpet!
> Though if you mean, the analog ground, the digital ground, and the plane are
> three separate nets that connect at one common point only, then yes, I
> agree.

I think at sdiy frequencies meaning anything below 25MHz. Layout
hardly comes into play below these frequencies, at least the kind of
layout work I'm used to now.

Usually plane splits occur when you have a highly noisy digital system
next to a very quiet analog system. The noise becomes a problem when
you have high-speed memories like SRAM and SDRAM hanging off of a
microprocessor, or other similar large-bus peripherals. You have a lot
of high-speed digital waveforms as well as the ICs sinking power from
the supply rails/planes. This causes a bunch of noise, however I have
yet to see a SDIY design operating at 25MHz with a bunch of 16-bit+
digital peripherals hanging off of a CPU. Most hybrid designs (minus
the FPGA ones folks are getting fond of) use an integrated
microprocessor like a PIC or an AVR. Most of the I/O is PWM or TTY
speeds in the 5-10MHz arena, which isn't too bad for plane separation
if you layout your boards carefully.

Just my $0.02,

Joe