[sdiy] website update - VC-Delay

[Colin Hinz]

On Thu, 15 Jul 2004, Nils Pipenbrinck wrote:

> Ryan's circuit made me think.... I doubt that the delay chip does any
> complicated acesses to the ram: Most probably it just alternates between
> write a byte and read a byte.. maybe even with a fixed address offset or
> no offset at all.
>
> If we would ignore the internal address-logic of the chip and roll our
> own we could make the delay time as small as we would like to, right?
> Can't be that complicated. I doubt we'll need much more than some
> counters and a binary adder.
>
> So, does anyone knows the ram access pattern of the PT2395?

The PT2395 uses a single-bit DRAM, so an emulation of its memory
interface would also require address multiplexing, refresh circuitry,
and a boatload of timing logic. If you're going to go through all
that, just interface an audio codec and some RAM to an FPGA and
write the delay circuit of your dreams!

- Colin Hinz
  Toronto, Canada