[sdiy] website update - VC-Delay

[Theo]

The RAM addressing is probably straight forward.
If I had to do it I would first read the delay-ed data and than write the
new "sample" to the same address.
However the CAS/RAS multiplexing is why lifting address lines don't work,
even in the simple scenario above.
They may write both CAS and RAS for every access or use burst mode and only
write CAS on a new cycle of the RAS counter.
Monitoring the CAS line with a scope would tell you.

Anyways, to drop address lines you (probably) need to do so for CAS only.
Some gates that block part of the CAS data might work.
That would need 2 or 3 standard TTL ICs.

Also completely other variation comes to mind.
Use two delay ICs, one with a fixed delay the other with VC.
That would result in a direct signal with a delayed chorus, could be a nice
effect in it self.
Using some smart audio routing the same unit also may do more complicated
delay work.

When doing the above, the shortest delay of the chorus would be around 33ms.
Don't know if 33ms or so "latency" of the chorus would be a problem.
Walking on thin ice here, but cause the "latency" is under the 50ms,
chorus and direct signal may be perceived as one.

Just me 2 cnt.

Theo




----- Original Message -----
From: Ryan Williams <destrukto at cox.net>
To: <synth-diy at dropmix.xs4all.nl>
Sent: Thursday, July 15, 2004 7:00 PM
Subject: Re: [sdiy] website update - VC-Delay


>
>
> I originally planned on doing another chorus type circuit using a few of
> these but couldn't figure out how to shorten the RAM size. It was
> suggested that it could be done by simply disconnecting address lines. I
> tried that and couldn't get it to work and left it at that because I
> wanted to finish my module and move on to something different. If anyone
> figures that out, I would like to hear about it.
>
> but, I had another idea that might work out. that is to put a similar
> circuit in a FGPA. it's more expensive and alot more work but I plan on
> trying this after I finish my digital IC design course and also finish
> some other projects and save enough money for a development board (that
> might be a while). I suppose it would be easier to find out what the RAM
> access pattern of that PT2395 is.
>
> -ryan
>
> Nils Pipenbrinck wrote:
>
> > Ryan's circuit made me think.... I doubt that the delay chip does any
> > complicated acesses to the ram: Most probably it just alternates between
> > write a byte and read a byte.. maybe even with a fixed address offset or
> > no offset at all.
> >
> > If we would ignore the internal address-logic of the chip and roll our
> > own we could make the delay time as small as we would like to, right?
> > Can't be that complicated. I doubt we'll need much more than some
> > counters and a binary adder.
> >
> > So, does anyone knows the ram access pattern of the PT2395?
> >  Nils
>
>
>