[sdiy] website update - VC-Delay

[Ryan Williams]

I originally planned on doing another chorus type circuit using a few of 
these but couldn't figure out how to shorten the RAM size. It was 
suggested that it could be done by simply disconnecting address lines. I 
tried that and couldn't get it to work and left it at that because I 
wanted to finish my module and move on to something different. If anyone 
figures that out, I would like to hear about it.

but, I had another idea that might work out. that is to put a similar 
circuit in a FGPA. it's more expensive and alot more work but I plan on 
trying this after I finish my digital IC design course and also finish 
some other projects and save enough money for a development board (that 
might be a while). I suppose it would be easier to find out what the RAM 
access pattern of that PT2395 is.

-ryan

Nils Pipenbrinck wrote:

> Ryan's circuit made me think.... I doubt that the delay chip does any 
> complicated acesses to the ram: Most probably it just alternates between 
> write a byte and read a byte.. maybe even with a fixed address offset or 
> no offset at all.
> 
> If we would ignore the internal address-logic of the chip and roll our 
> own we could make the delay time as small as we would like to, right? 
> Can't be that complicated. I doubt we'll need much more than some 
> counters and a binary adder.
> 
> So, does anyone knows the ram access pattern of the PT2395?
>  Nils