[sdiy] Frequecy Divisor Question (TTL pulse stretcher needed)

[Michael Buchstaller]

>Hmmm...  by the time that 5 ns pulse gets done propogating around the
>board to all of the places it needs to go, the signal probably looks
>kind of nasty.  

Goot point here. But luckily the signal goes only from the carry output of one
counter to the clock input of the next one - just a very short distance. Inside the counter,
it is kind of "refreshed" by the things the logics inside are doing to the signal.

The only long line with several taps is the "Load" input of all counters, which is
paralleled and driven from my pulse stretcher. I cannot measure if the pulse is there
without it, or if not. But with stretching it does work fine.

OK. the stretching messes up the timing, because i loose 4 clock cycles every time,
but i have taken this into account when reading the note data from the LUT in software.

>... When I was at Gould in the mid-80s
>and they did everything in ECL, they used terminating resistors
>of 50-100 ohms on nearly every trace on each board....

Maybe it would be still a good idea to terminate the "Load" wire at the end far away from the
pulse stretcher that drives it. Just in case...


-Michael Buchstaller