Odp: [sdiy] FIFO as memory buffer

[jbv]

Roman,

> If I may suggest something completely different...
>

Thanks for the suggestions, but I've already
explored such possibilities and finally decided
to forget them for several reasons, the main
ones being : I can't afford to waste CPU cycles
in managing timers / interrupts, I don't have
any free serial port, and a multiplication of buses
can quickly become a headache in terms of PCB design...

I think I'll finally go with the double FIFO solution :
it's quite brute force solution, but it's also the most
cost efficient in terms of # of chips, # of buses and PCB
room...

JB