Odp: [sdiy] FIFO as memory buffer

[Roman Sowa]

If I may suggest something completely different...

if your uCs have unused serial ports, you can connect
them all and establish something like a local bus. Say, master
wants to send something to slave no. 5. It sends a address byte
with 5 in it, and then data. Either 1 byte, or block of bytes,
that could be determined in addres byte too. uCs listen
to serial port and if they see their address, they read it all.
Others take into account that they must ignore next 'n'
following bytes and listen for an address again.
Slave->master is more complicated and there can be various
ways to avoid collision. Say, master issues one pulse every
8ms or so. Then all slaves set their timers to following mss.
1st to 0, 2nd to 1ms... 8th to 7ms. When the timer expires
the slave sends all what it has to send, and then tri-states
its serial port output. Master knows who was originator
by the time of the event.
Or if there's 8 available pins (or 3 with HC138) you can
ping every slave and it will then send the data when asked.

Or another approach:
Bus arbiter. Normally master has access to common
memmory. If there is request from slave, an interrupt is
issued for master. It then can decide who will go first
if there's more than 1 requests at the time, and grants
the access. Slave rises a flag (wire-ORed pin or whatever)
and all, including master wait for end of transmission.
When it ends, master reads what slave has just written.
Then it can grant access to another slave.
That requires data and address bus to be shared by
9 uCs. It could be done as 2 8-bit I/O ports for
example. And 1 additional port for controlling slaves.

Some uCs have multiprocessor communication implemented
in hardware. The one that comes to mind is SHARC DSP.

Roman

----- Original Message ----- 
From: jbv <jbv.silences at club-internet.fr>
To: <synth-diy at dropmix.xs4all.nl>
Sent: Saturday, March 08, 2003 1:59 PM
Subject: [sdiy] FIFO as memory buffer


> Does anyone have any experience using FIFO RAM
> as memory buffer between 2 microcontrollers ?
> 
> I'm presently brainstorming on a project featuring
> 1 uC as master and several other uCs as slaves.
> The master would pass data to slaves through a
> memory buffer (1 for each slave), and would then
> collect results through the same buffer.
> 
> FIFO Ram looks like a perfect candidate for such
> a function, and I've found several datasheets
> (Cypress for instance).
> 
> But the problem is that FIFO works great when
> communication happens in 1 direction only (for
> instance master -> slave).
> Things get more complex when the same FIFO
> is supposed to be used in both directions...
> In my project, reading & writing times will never
> overlap (neither for master nor slave)...
> 
> Of course, I could probably find a solution by
> adding bi-directional buffers and a few logic gates
> to the FIFO...
> But I was wondering if there were any FIFO chip
> that would reverse i/o with only 1 control pin...
> And in DIL package if possible...
> 
> Am I asking too much ?
> 
> Thanks,
> JB
> 
>