Lpc2000

No, that's entirely correct.  One solution is to bake the parts.  
We've had to do this a number of times where we use sealed packs for an 
initial build, then build from the same stock several months later.  Our 
manufacturing company doesn't have climate controlled storage, so ICs 
and a few parts get baked as a precaution.  I think they use something 
like 125F for 4 or 8 hours.  I've seen the ovens, but I don't remember 
the temperature profiles.

    From what I understand, the most common failure mode is the bond 
wire from the die to the pin breaking.  I've never seen external 
physical evidence of cracking, at least, not with the microscopes I've 
had at my disposal.  I would imagine that most of the damage should 
occur internally, where the moisture expands before it can out-gas.  
Near the edge of the package, it would escape before it could expand far 
enough to leave evidence around the pins.

    It would be neat to see some photo-micrographs of parts known to be 
damaged this way.  Other than parts being misregistered, installed 
backwards, or boards that sustained mechanical damage (like getting 
caught in a misadjusted feed chain...)  I've never seen a chip that I've 
known to be damaged in manufacturing, i.e., from static or humidity 
issues.  However, manufacturing is not my regular job, so I'm only 
around the manufacturing lines a couple times a year, and usually 
fine-tuning the test jigs.

    Most of my exposure to the rest of the process is providing feedback 
to the manufacturing manager when I find boards with consistent sets of 
problems.  Since we don't run boards in huge quantities, we don't get 
the advantage of getting a line setup and tuned and cranking out 
thousands of flawless boards.  We typically run 100 to 500 at a time, 
and it usually takes 50 boards or so to get all the placements right and 
the temperature profiles set.  We also use a board house that does small 
runs, which means we get human inspection, and these people are far from 
flawless.

    --jc

Joseph Tapay wrote:

> excellent resource, thanks JC
> i've noticed the shortness of the philips' solder land, so far no 
> rationale
> to justify it...
> philips' drawing shows two different width for start/end of row/column
> (0.30mm) and in between (0.23mm) for LQFP64 package, which is relevant to
> this group, IPC 565A landing pattern (IPC parlance versus philips
> "footprint") does not differentiate, hmmm... interesting...
>
> The solder vaporphase reflow/IR reflow may explain our problem to obtain
> chips in quantities of 10. The chip will aquire the temperature of the
> solder. Presence of moisture inside the package could cause cracking of
> housing. So they get shipped in dry packs containing 250 chips. The
> distributor is paralyzed into no action fearing to break the drypack!
> This is a hypothesis of course, anybody has one better?
>
> j