Lpc2000

Something is odd here. I can't think of a reason why the address is loaded 
with 3 instructions. One optimization we are considering is to cache the 
base address in a register, but this is not it. In either ARM or Thumb 
mode, the shortest sequence is something like this:
         mov R0,#68
         ldr R1,LIT_main+0
         str R0,[R1,#0]

Pipelining doesn't do anything in this regard. Using 3 instructions instead 
one in the same processor with sane instruction cycles is never going to be 
a win :-)

At 12:59 PM 8/26/2005, you wrote:

>y4krys wrote:
>
> > Brian,
> > This is how it looks compiled with my tools in the THUMB mode:
> >
> > //  PLLCFG  = (4 + (2 << 5));
> >
> > 0x0000015E 4812 LDR R0,[PC,#0x048]  ; [0x1A8] =_A_PLLCFG (0xE01FC084)
> > 0x00000160 2144 MOV R1,#68
> > 0x00000162 6001 STR R1,[R0, #0]
> >
> > My compiler has allocated a constant (address of PLLCFG) at 0x1A8 to
> > avoid the limitation of the immediate operand size.  It looks like
> > your compiler prefers code generation over the data allocation.  Not
> > all compilers are made equal ;-)).
> >
>
>When I optimize for size this is what CrossWorks generates.
>
>Thanks,
>
>Brian
>--
>-----------------------------------------------------
>Brian C. Lane (W7BCL)                      Programmer
>www.shinemicro.com   RF, DSP & Microcontroller Design
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// richard (This email is for mailing lists. To reach me directly, please 
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