Lpc2000

Hi Ken,

we did some measurements of code ranging from mostly linear execution
(best case) to pretty much jump tables with very little linear code
(worst case). If the code is mostly linear (let's assume one branch
every 20 instructions or less), execution from RAM and execution from
Flash were virtually identical, 99+% performance from Flash. In
particular loops that are not nested do not cause wait states. This
might not be realistic for larger programs but it could be close to a
small DSP control loop.

Code with lots of branches and no loops was slower by approx. 10-15%
running from Flash compared to running from RAM. Unfortunately I can
not provide the programs used, they are part of a benchmark suite that
needs a license. This second program is designed to show performance
without cache (it is called cache-buster ;-). IMHO it is not very
close to realistic code and generates performance numbers worse than
average code. 

Realisticly, we see operation from Flash (@ 60 MHz) approx. 95% of the
performance compared to running from RAM. This looks extremely good to
us and the claimed "0-waitstate execution"  can pretty much be
confirmed. It is much closer to 0 waitstates than to 1 waitstates,
let's call it a rounding error.

Cheers, Bob

--- In lpc2100@yahoogroups.com, "kendwyer" <kendwyer@y...> wrote:
> --- In lpc2100@yahoogroups.com, "Leon Heller" <leon_heller@h...> 
> wrote:
> > > Hi all 
> > >  
> > > Dose any one know how many MIPS can the lpc2106 do @ 60Mhz ?
> > 
> > Philips claims 54 Dhrystone MIPS at 60 MHz:
> > 
> > 
> http://www.semiconductors.philips.com/acrobat/literature/9397/75011962
> .pdf
> > 
> > Leon
> 
> This is an ideal theoretical number using Dhrystone. Has any one done 
> some real world benchmarking? How effective is the flash "cache" with 
> real code?