Lpc2000

At 08:46 AM 1/9/05 +0000, you wrote:
>I've had the UARTs on the LPC21xx LPC22xx running fine at 115.2k (e.g.
>receiving large files with 32 bit CRCs). It just that the divisor
>arrangement means the baud rate @ 12MHz is approx 1% out (with the PLL
>multiplying the XTAL by 5 to 60MHz / VPBDIV = 1). I just wondered
>whether the bootloader on the chip gives up if it can't get an exact
>baud rate...

Remember the ISP program on chip doesn't use the PLL (at least there is no 
indication that it does) so a 1% mismatch at the (pll'd) 60MHz could be a 
5% mismatch at 12MHz native clock.  You can see the problem.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III