Lpc2000

Hi Andreas,

I did as you suggested and the SPI works correctly at much higher 
speeds.  Thank for your help.  This still leaves me with the problem 
of a chip select signal generated by GPIO that is extremely slow and 
if I follow a set too closely behind a clear, I never see the low 
state on the signal line. Am I also doing something wrong with the 
GPIO.  When I step through the code for manipulating the GPIO signal, 
it works as I expect.

Thanks,
Bob Davis

--- In lpc2000@yahoogroups.com, "haack0815" <lpc_arm@s...> wrote:
> Hi Bob,
> 
> the maximum SCLK of the SPI Interface is 1/8 of pclk.
> 
> If cclk is 60MHz and pclk = cclk you get a maximum SCLK speed of 
7.5 MHz.
> 
> 
> It seems that your cclk is 14.7 Mhz and pclk is 1/4 of cclk.
> Setup your PLL and VPBDIV Register to the right values.
> 
> Andreas