Lpc2000

> Hi
> Thanks to all of you who replied, and thanks for the suggestions. I 
> am plugging away at the moment to get a test bench working to 
> incorporate them. I did try the quick-stab approach which failed 
> miserably so I am now doing it properly.
> 
> To answer the last questions, all I need is simple read/write access 
> over an 8-bit bus. No multi-master or different bus widths to 
> contend with, so I was hoping that it would be straightforward.
> 
> It should all make a bit more sense once I have it running in the 
> simulator.
> 

Hey Simon,

 > so I am now doing it properly.

Good for you!

I took a quick look at the data sheet, and it really doesn't
look too hard. The FPGA either needs to look like SRAM, which the
dual-ported SRAM in the FPGA can do quite nicely, or a
clocked register could be made to work as well. You might
just have to setup the LPC wait-states.

The downside of the LPC implementation of their external bus
interface is that you can't force the processor to wait for a
variable number of cycles (via a WAIT# input pin).
eg. lets say you wrote an SPI controller in the FPGA, if
you could extend the processor read cycle, then you can
force the read to take as a long as the SPI transaction.
However, the solution is to make sure you route an interrupt
line between the LPC and the FPGA, and then you start a
transaction by writing to a register, then poll for done,
or use an interrupt, then read the result. In each case,
access is to a register, so the timing on the bus is
identical.

Cheers
Dave