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troubleshooting Dual CMOS VCF

2009-10-11 by Jan-Ahrent Czmok

Hi there,

got some issues with my finished CMOS VCF:

-15V to ground -- 41.9k
+15v to gnd -- not measureable (but not 0)

When connected to the modular, i get a short.

Stange is: before i connected ground to the GND panel, the module
seemed to work.

Any ideas ?

--jan

Re: troubleshooting Dual CMOS VCF

2009-10-11 by Dave Kendall

a shot in the dark here - bad decoupling capacitor on the neg rail?

cheers,
Dave

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On Oct 11, 2009, at 11:56, Jan-Ahrent Czmok wrote:

> Hi there,
>
> got some issues with my finished CMOS VCF:
>
> -15V to ground -- 41.9k
> +15v to gnd -- not measureable (but not 0)
>
> When connected to the modular, i get a short.
>
> Stange is: before i connected ground to the GND panel, the module
> seemed to work.
>
> Any ideas ?
>
> --jan
>
>
>

Re: troubleshooting Dual CMOS VCF

2009-10-12 by Jan-Ahrent Czmok

On 11.10.2009, at 18:48, Dave Kendall wrote:

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> a shot in the dark here - bad decoupling capacitor on the neg rail?
>
> cheers,
> Dave

i changed two caps and now its (kind of ) working.

the VCF does close to 90% on the LP but it seems HP is always open
as similar on notch. behaviour is similar on the other vcf .

any ideas ? i assume the trimmers are for the CV SPAN , right ?

--jan

Morph-Lag

2009-10-12 by Andrew Scheidler

Building a Morph-Lag, and have two questions:

1) The PCB specifies that C1 (see schemo below) is a "5uF MYLAR". Will a standard poly cap work OK? Or some other type?

http://www.wiseguysynth.com/larry/schematics/Morph-Lag/Morph-Lag.gif

2) If I was to use 500k pots for the Attack & Decay (instead of the 1M specified), would that just limit the max lag to a shorter time?

thanks :)
Drew

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Re: Morph-Lag

2009-10-12 by Ove Ridé

2009/10/12 Andrew Scheidler <oozitron@...>:

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> Building a Morph-Lag, and have two questions:
>
> 1) The PCB specifies that C1 (see schemo below) is a "5uF MYLAR". Will a standard poly cap work OK? Or some other type?
>

It's a simple low pass filter so I'd guess the type is non-critical,
except that it can't be any polarized type. A polarized capacitor will
get charged in reverse and explode (worst case scenario) or leak
current if you charge it in the wrong direction. (Best case scenario)
Also, I wonder why it says 5 uF rather than 4.7 uF. (Which is a
standard E12 series value) Nothing wrong with it, just peculiar.

> http://www.wiseguysynth.com/larry/schematics/Morph-Lag/Morph-Lag.gif
>
> 2) If I was to use 500k pots for the Attack & Decay (instead of the 1M specified), would that just limit the max lag to a shorter time?
>

Correct. Because of the way the pot is connected, the 500k max value
is just a subset of the full 1M range.

--
/Ove

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troubleshooting Dual CMOS VCF

troubleshooting Dual CMOS VCF

Re: troubleshooting Dual CMOS VCF

Re: troubleshooting Dual CMOS VCF

Morph-Lag

Re: Morph-Lag

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