Hi list,
I recently posted this at the SergeModular Yahoo group, but it was suggested that here might be a better place, so here goes!:
I'm trying to simulate the Negative Slew from this schematic:
http://www.cgs.synth.net/synth/serge/pic/serge_negative_slew_schem.gif
I'm trying to investigate how well the CV controls the negative slope, but I
can't get the simulation to run properly, mainly because I can't see how on
earth the main integrator (amp pins 8/9/13) resets: for this to happen base 6
will need to climb to about 2 diode drops above ground, but I simply see no
route for any current to enter the 220k there - all the diode junctions in the
two transistors would appear to prevent this. Anybody know if this schematic is
accurate, or can explain how it does work (if indeed it does)? (I've checked
that part of the circuit against the PCB layouts given in other pics there, and
they look like they agree.)
I also think the (kind of) 'diode connected' transistor 9/10/11 would cause
grief to the CA3086 if the 'diode' could in fact conduct: this would effectively
put the transistor into saturation, which might be bad news for the chip, as I
think it would turn on the parasitic PNP transistor (formed from
base-collector-substrate), causing current to flow out of the substrate.
Has anyone any thoughts or ideas?
Thanks, Tim
__________________________________________________________
Tim Stinchcombe
Cheltenham, Glos, UK
www.timstinchcombe.co.uk
I recently posted this at the SergeModular Yahoo group, but it was suggested that here might be a better place, so here goes!:
I'm trying to simulate the Negative Slew from this schematic:
http://www.cgs.synth.net/synth/serge/pic/serge_negative_slew_schem.gif
I'm trying to investigate how well the CV controls the negative slope, but I
can't get the simulation to run properly, mainly because I can't see how on
earth the main integrator (amp pins 8/9/13) resets: for this to happen base 6
will need to climb to about 2 diode drops above ground, but I simply see no
route for any current to enter the 220k there - all the diode junctions in the
two transistors would appear to prevent this. Anybody know if this schematic is
accurate, or can explain how it does work (if indeed it does)? (I've checked
that part of the circuit against the PCB layouts given in other pics there, and
they look like they agree.)
I also think the (kind of) 'diode connected' transistor 9/10/11 would cause
grief to the CA3086 if the 'diode' could in fact conduct: this would effectively
put the transistor into saturation, which might be bad news for the chip, as I
think it would turn on the parasitic PNP transistor (formed from
base-collector-substrate), causing current to flow out of the substrate.
Has anyone any thoughts or ideas?
Thanks, Tim
__________________________________________________________
Tim Stinchcombe
Cheltenham, Glos, UK
www.timstinchcombe.co.uk