Tim,
Ken runs a Yahoo group (cgs_synth) for the discussion of the stuff on his site. You may want to post over there. He's typically very helpful and responsive. In fact please do as I'm very interested in the workings of these circuits...
-dustin
Ken runs a Yahoo group (cgs_synth) for the discussion of the stuff on his site. You may want to post over there. He's typically very helpful and responsive. In fact please do as I'm very interested in the workings of these circuits...
-dustin
--- In SergeModular@yahoogroups.com, "Tim" <timothy@...> wrote:
>
> Hi list,
> I'm trying to simulate the Negative Slew from this schematic (I'm assuming drawn by Ken - is he around these parts?):
>
> http://www.cgs.synth.net/synth/serge/pic/serge_negative_slew_schem.gif
>
> I'm trying to investigate how well the CV controls the negative slope, but I can't get the simulation to run properly, mainly because I can't see how on earth the main integrator (amp pins 8/9/13) resets: for this to happen base 6 will need to climb to about 2 diode drops above ground, but I simply see no route for any current to enter the 220k there - all the diode junctions in the two transistors would appear to prevent this. Anybody know if this schematic is accurate, or can explain how it does work (if indeed it does)? (I've checked that part of the circuit against the PCB layouts given in other pics there, and they look like they agree.)
>
> I also think the (kind of) 'diode connected' transistor 9/10/11 would cause grief to the CA3086 if the 'diode' could in fact conduct: this would effectively put the transistor into saturation, which might be bad news for the chip, as I think it would turn on the parasitic PNP transistor (formed from base-collector-substrate), causing current to flow out of the substrate.
>
> Has anyone any thoughts or ideas?
>
> Thanks, Tim
> __________________________________________________________
> Tim Stinchcombe
>
> Cheltenham, Glos, UK
> www.timstinchcombe.co.uk
>
