SergeModular

--- In SergeModular@y..., "Sebastian Kuehnl" <skuehnl@y...> wrote:

> Hello John, Peter and all,
>
> From JohnP:
>
> > The stepped part of the SSG doesn't 'self-clock'. Not mine

anyway... the

> > CYCLE jack I believe is meant to be patched back to the IN jack.

Then

> > when
> > you clock the SAMPLE (with a periodic clock) you get a weird

staircased

> > triangle, the stairstep relative size determined by the rate

knob. Slow

> > rate
> > = many small stairsteps = close approximation to triangle, fast

rate =

> > few,
> > large stairsteps = jerky square-edged poor approximation to

triangle. So

>
>
> I've looked at the SSG again and really the only way to

get "bitrate"

> control of a signal in the Serge system would be to generate steps

in a slew

> limiter output artificially via voltage control.
>
> this is easy controlling a track-and-hold function like on the SSG

Smooth

> section, and can also be done with a simple VC slew limiter module -

given

> the "hold" input (resp. the lag CV input) can react to high (mostly
> ultrasonic) frequencies:
>
> For normal slew limiters:
> Flip back and forth (that is, the CV to do this must be "1 bit"

itself :->)

> between no lag/ lag (required lag length theoretically infinite, but
> practically depends on input frequency) certain times per (full

amplitude)

> phase, for example 32 "holds" per phase = 4 bit output,

4096 "holds" = 12

> bit output etc.
>
> For the Smooth FG simply, "hold" input going high times per phase.
>
> But so far we can only establish arbitrary, non-steady "bitrates".

Any

> efficient suggestions as to how to *efficiently* determine and to

detect the

> tresholds for flipping/ holding at precise rates, using nothing

than the

> Serge (remember, we can get low bitrate easier..) are welcome.
>
> I don't think envelope followers are fast enough. So here's mine:

rectifying

> (phase doubling) a copy of the SmoothFG signal input 32 (or 4096,

or 65536

> or...) times, using this multiplied signal (I said ultrasonic even

before!)

> to clock an S&H which samples another copy of the SFG input (the

clock might

> need to be overdriven to have a steep enough edge), OR-ing the S&H

out and a

> nother copy of the SFG input, finally use OR gate for the

SmoothFG "hold"

> input... Hah, now you got bitrate control at the SmoothFG output.
>
> ;-p
>
>
>
> Sebastian Kuehnl
>
>
>
> > it's, like, self-sampling an internally generated triangle, but

the clock

> > still has to be provided from an external source.
> >
> > You CAN clock the stepped part by patching the smooth part CYCLE

jack to

> > IN
> > jack so it oscillates, then patch IN to SAMPLE on the stepped

part.....

> > strange thing though, you get TWO triggers per smooth cycle.
> >
> > My SSG is vintage 1997, Rex Probe, STS. Does anybody else's

behave

> > differently?
> >
> > John P.
> >
> >
> >
> >
>
>
>
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