AVR-Chat

poitsplace wrote:

[snip]

> CONSIDERING that the amount of space it would
> take to replicate that same latch on the die
> of a SRAM chip is smaller than a grain of
> salt...why the hell hasn't someone pulled
> their heads out of their posteriors long
> enough to see that there's a very real NEED
> for a parallel SRAM, Flash and EEPROM with
> a multiplexed data/address bus???

Of course it could be done, much better than that, they could include some
non-volatile protection, incorporating a NVBattery input pin, and more,
include a real time clock in there, and having a communication protocol and
available electronics, they could include a thermal sensor, cost by cost it
could be very cheap since nothing fancy was implemented.  But it would
require 3 or 4 communication cycles to input data, addresses, get data back,
etc.  Then, if processor cycles is not that much important nowadays with the
fast AVR available, then why not take all the parallel thing away and
implement everything in a single wire?  The processor who does 4 cycles to
read something could do 25 cycles in fast clock and space will be saved more
and more. Perhaps this is they invented SPI memories...

I agree with you.  Latched SRAM would be a real nice thing. Instead to use
/OE and /CE they could switch it to /CE1, /CE2, combination of those would
select;  00 = Address Latch1, 01 = Address Latch2, 02 = Data Latch Read, 03
= Data Latch Write. Thats it.

Wagner.


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