Never mind. When I wrote up the problem it was staring me in the face. I guess it is getting to late. SIGNAL(SIG_INPUT_CAPTURE3) is supposed to be SIGNAL(SIG_OVERFLOW3) -----Original Message----- From: AVR-Chat@yahoogroups.com [mailto:AVR-Chat@yahoogroups.com] On Behalf Of wbounce Sent: Saturday, May 28, 2005 12:17 AM To: AVR-Chat@yahoogroups.com Subject: [AVR-Chat] Avrstudio debug question I am using winavr 3.4.1 with AVR studio 4.1. I am trying to find out why my code is no longer driving my motors. Anyhow I am stepping through it in AVR Studio and every so often I get jumped to the default interrupt vector. I have defined a default interrupt routing that just return. (I did this because otherwise it would just reset the MCU.) I think this may be related to my problem. I have the following interrupts defined SIGNAL(__vector_default) SIGNAL(SIG_INTERRUPT6) SIGNAL(SIG_INTERRUPT5) SIGNAL(SIG_OUTPUT_COMPARE0) SIGNAL(SIG_INPUT_CAPTURE3) SIGNAL(SIG_UART0_RECV) SIGNAL(SIG_UART1_RECV) SIGNAL(SIG_UART0_TRANS) SIGNAL(SIG_UART1_TRANS) In the I/O panel the following items are in red (meaning changed on the last single step TCNT3L ETIFR (OCF3A, OCF3B,OCF3C are set) (listed under Timercounter3) ETIFR (none are set) (listed under Timercounter1) This would suggest something related to timer3 Here is my relavant code for timer 3 TCCR3A = BV(WGM31) | BV(WGM30); /* set timer/counter 3 to PWM mode 3 */ TCCR3A |= BV(COM3A1) | BV(COM3B1); /* Clear OCnA/OCnB/OCnC on compare match when up-counting. Set OCnA/OCnB/OCnC on compare match when downcounting.*/ TCCR3B |= BV(CS30) ; /* prescale: 1 @ 16 MHz, 10 bit PWM overflows @ 15625 Hz giving 7812 HZ */ ETIMSK |= BV(TOIE3); // enable overflow interupt so we can set pwm in int routine Does anyone see anything wrong? Yahoo! Groups Links
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RE: [AVR-Chat] Avrstudio debug question Never mind
2005-05-28 by wbounce
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