AVR-Chat

Hello everyone,
After just subscribing to AVR-chat I will introduce 
myself by asking a question - hopefully nobody minds.

My upcoming design involves two CPUs that need to share rather large 
areas of memory - both reading and writing. Lately, 32kByte shared
mem 
have been considered enough and so I sit and think about how to do it 
using two AVRs.

Dual ported RAM is way too expensive and hard to get (considering
that 
128Kx8 can be had in under $1 a pop) and so focus is on stuff like 
628128-70. This is a 128Kx8 SRAM available in SOP-32 with seperate 
data and memory bus pins, /OE and /WE. The data bus is bidirectional 
and only driven during read operations (== /OE low).

Interfacing with an ATmega128 (M128) is usually done using a 74x573 
latch (as outlined in the data sheet) with its ouput always enabled 
and its Latch Enable tied to M128's ALE.

Now comes the tricky part: As soon as I hook up the additional second 
M128 (and corresponding latch), I get logical and electrical
problems. 
What bugs me more are the electrical implications. As A7:0 and D7:0 
are shared on the AVR-side I need to make sure that both AVRs'
latches 
do not drive their outputs while one AVR makes a read operation. My 
idea is to tie the latch's /OE from M128s /RD.

There will of course be a software-guided scheme that ensures mutual 
exclusive access to the external SRAM. This includes lower the
initial 
stack pointer to use internal SRAM, having interrupt-used variables
in 
internal SRAM too and only accessing external RAM explicitly.

But what if one AVR runs amok? Say errant software or hardware
failure 
results in a read strobe to SRAM while one AVR lets its latch drive 
D7:0? Then one may drive 0 while one may drive 1 -> high current. Is 
it possible and enough to limit the maximum current using series 
resistors that lower the current to less than the absolute maximum 
ratings of all chips? Will this significantly reduce speed?

Did you ever try this or have comments?

Thanks in advance.

-- Philipp