AVR-Chat

Dave VanHorn wrote:
> 
> At 04:29 PM 3/1/2005, John Samperi wrote:
> 
> >At 08:18 AM 2/03/2005, you wrote:
> >
> >
> > >Well, it's still got me.
> > >
> > >USART1 continuously hits me with a TXD int, even though it's not enabled.
> >
> >Hmmm... I was just asking about that...perfect timing.
> >Have you tried just to run your code WITHOUT the ICE?
> 
> Yup. I put a pin-ping in there so I can see the ISR happening, and it's
> still there.
> 
> >NOT that I doubt the fuctionality of the ICE or Studio 4.xx
> >of course.......
> 
> Oh never.. :) (gag sputter)
> 
> >  Perhaps put some led toggling code in that
> >int service just to see if you are really getting the int
> >from the chip or just the ICE/Studio combo.
> 
> It almost looks like my vector table is wrong or something, but I've
> counted the entries, and checked it against the one in the data sheet.  It
> really ACTS like a UDRE int, or "level" int on one of the pins, those are
> the only ones I'm aware of that will hit you every instruction until they
> are turned off, or the trigger condition dissapears.


Sounds like fun. Try including my default vector table stuffer and see who 
bangs the bogus counter. (You may need to change what is commented out and
what isn't.) BTW, this for ICCAVR, anything else will need some editing...

Bruce

default_isrs.c:

// default M128 interrupt service routines

// these routines, when executed, mask off the request and
// tally the bogus interrupt

// delete or comment out if used elswhere...

#include <iom128v.h>

unsigned bogus;     // tally count

#pragma interrupt_handler int0_isr:2
void int0_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF0);
}

#pragma interrupt_handler int1_isr:3
void int1_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF1);
}

#pragma interrupt_handler int2_isr:4
void int2_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF2);
}

#pragma interrupt_handler int3_isr:5
void int3_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF3);
}

// CompactFlash Status Change Interrupt
/*
#pragma interrupt_handler int4_isr:6
//void int4_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF4);
} */

/* CompactFlash Command Complete Interrupt

#pragma interrupt_handler int5_isr:7
//void int5_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF5);
} 
*/

// Bridge Interrupt 0

#pragma interrupt_handler int6_isr:8
void int6_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF6);
}

// Bridge Interrupt 1

#pragma interrupt_handler int7_isr:9
void int7_isr(void)
{
    ++bogus;
    EIMSK &= ~(1 << INTF7);
}

#pragma interrupt_handler T2comp_isr:10
void T2comp_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << OCIE2);
}

#pragma interrupt_handler T2ovf_isr:11
void T2ovf_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << TOIE2);
}

#pragma interrupt_handler T1capt_isr:12
void T1capt_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << TICIE1);
}

// 1 mS ticker
/*
#pragma interrupt_handler T1compA_isr:13
void T1compA_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << OCIE1A);
}
*/

#pragma interrupt_handler T1compB_isr:14
void T1compB_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << OCIE1B);
}

#pragma interrupt_handler T1ovf_isr:15
void T1ovf_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << TOIE1);
}

#pragma interrupt_handler T0comp_isr:16
void T0comp_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << OCIE0);
}

#pragma interrupt_handler T0ovf_isr:17
void T0ovf_isr(void)
{
    ++bogus;
    TIMSK &= ~(1 << TOIE0);
}

#pragma interrupt_handler SPI_isr:18
void SPI_isr(void)
{
    ++bogus;
    SPCR &= ~(1 << SPIE);
}

#pragma interrupt_handler UART0rx_isr:19
void UART0rx_isr(void)
{
    ++bogus;
    UCSR0B &= ~(1 << RXCIE0);
}

// com-0 Tx Rdy
/*
#pragma interrupt_handler uart0_udre_isr:20
void uart0_udre_isr(void)
{
    ++bogus;
    UCSR0B &= ~(1 << UDRIE0);
}
*/

// UART-0 Tx Empty

#pragma interrupt_handler uart0_tx_isr:21
void uart0_tx_isr(void)
{
    ++bogus;
    UCSR0B &= ~(1 << TXCIE0);
}

#pragma interrupt_handler adc_isr:22
void adc_isr(void)
{
    ++bogus;
    ADCSRA &= ~(1 << ADIE);
}

#pragma interrupt_handler eerdy_isr:23
void eerdy_isr(void)
{
    ++bogus;
    EECR &= ~(1 << EERIE);
}

#pragma interrupt_handler ana_comp_isr:24
void ana_comp_isr(void)
{
    ++bogus;
    ACSR &= ~(1 << ACIE);
}

#pragma interrupt_handler T1compC_isr:25
void T1compC_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << OCIE1C);
}

#pragma interrupt_handler T3capt_isr:26
void T3capt_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << TICIE3);
}

#pragma interrupt_handler T3compa_isr:27
void T3compa_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << OCIE3A);
}

#pragma interrupt_handler T3compb_isr:28
void T3compb_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << OCIE3B);
}

#pragma interrupt_handler T3compc_isr:29
void T3compc_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << OCIE3C);
}

#pragma interrupt_handler T3ovf_isr:30
void T3ovf_isr(void)
{
    ++bogus;
    ETIMSK &= ~(1 << TOIE3);
}

// 31 RxRdy in serial_io.c
/*
#pragma interrupt_handler UART1RxRDY_isr:31
void UART1RxRDY_isr(void)
{
    ++bogus;
    UCSR1B &= ~(1 << RXCIE1);
}
*/

#pragma interrupt_handler UART1TxRDY_isr:32
void UART1TxRDY_isr(void)
{
    ++bogus;
    UCSR1B &= ~(1 << UDRIE1);
}

#pragma interrupt_handler UART1TxE_isr:33
void UART1TxE_isr(void)
{
    ++bogus;
    UCSR1B &= ~(1 << TXCIE1);
}

#pragma interrupt_handler TWI_isr:34
void TWI_isr(void)
{
    ++bogus;
    TWCR &= ~(1 << TWIE);
}

#pragma interrupt_handler SPM_isr:35
void SPM_isr(void)
{
    ++bogus;
    SPMCSR &= ~(1 << SPMIE);
}