Hi all
I've been studying the docs that Juergen Haible published on his site about Key coder and KAS...but I don't quite understand the logic underneath the algorythm...
We have 3 clocks on the kas main IC:
master clock (94.5KHz, that's +/- 0.9ms per cycle)
SC clock ( at 1/9 of master clock timing : +/- 10.5 KHz )
SC8 clock (at 1/8 of SC clock timing : +/- 1.31 KHz )
the Key coder detects the note and octave of pressed key and buffers it into a time-shared bunch of channels (11us for 1 note, 22us for 1+1note and so on to 88us for all 8 notes at one time ) then sends the key data to KAS
KAS features 2 gates (one receiving key data and one looped with shift register ) and a comparator to output the signal to SH board if I'm not wrong...
If I'm correct at note off status the shift register stores the data for -inactive-C4 key , the data is processed at "1 note clock" that's 11us and this data stays in all 8 channels cells of the shift register; at note on the data is processed at 1 note clock + 11us and so on....the question I need to understand is : keeping the clock references , what is the order in which the channels are outputted??
Please, let me learn something more.................
Max