[sdiy] Pole Mixing Multi-Mode filter design with SSI2140

Sat May 2 00:30:47 CEST 2026

Thanks for the input, John. This has been a fun project to work on in retirement—and something I’ve wanted to do since the 80s. I went back and checked my git repo history, and it goes back about three years!

Here’s a picture of the setup as it stands now. The firmware runs on an STM32H755ZIQ dual-core. At this point, I’m mostly implementing circuit designs from the SSI documentation—I don’t think I have the analog chops yet to go much beyond that. Filters, in particular, have been the most challenging when it comes to understanding whether they’re behaving as expected. When something doesn’t work correctly on the analog side, I can spend a lot of time scratching my head. Lately, I’ve been using AI to ask questions and get hints on where to look, which has been an interesting—and surprisingly helpful—part of the process.

Over the past year, I’ve also spent a good amount of time designing a control panel with encoders and buttons, along with a UI on an LCD display to tweak parameters in real time. I’ve added support for a touchscreen as well, which I’m hoping to explore next.

On the firmware side, I’ve designed the system to support four timbres and as many voices as I can manage within processing limits—mainly constrained by how quickly I can service the DACs and handle GPIO expanders for voice allocation. My goal is to reach around 24 voices with smaller boards and full surface-mount designs, but I’m taking it in stages so I can properly debug along the way.

Sent by voice-transit conductor

> On May 1, 2026, at 12:55 PM, John Speth via Synth-diy <synth-diy at synth-diy.org> wrote:
> 
> Firstly I'm impressed with your resourcefulness. It was a pleasure to read your post.
> 
> My background is just about the same as yours (EE then FW eng, retired) so my answer should be taken with some doubt. In theory, DC blocking caps should have no negative effect if there is no need for any DC bias. You'll need to make sure the AC impedance doesn't kill the low end of your desired frequency spectrum. In other words, calculating the right capacitance is important. The theory is easy. An experienced EE should be able anticipate any practical problems. I'm sure there are some.
> 
> Good Luck - John Speth
> 
> On 5/1/2026 8:08 AM, Jeff Whitman via Synth-diy wrote:
>> 
>> 
>> Hello there,
>> 
>> I’ve been working on an analog synth project for several years using Sound Semiconductor parts. Their data sheets and design notes have been incredibly helpful, especially for those of us who are not primarily analog designers. I’m a firmware engineer by profession - now retired, with an EE background from a long time ago, so I understand the basics but would really appreciate input from people with more analog design experience.
>> 
>> For this project, I’ve built a “voice” of three oscillator boards using the SSI2131, a filter board using the SSI2140 in the suggested pole-mixing configuration to create a 16-mode multimode filter, a low-pass filter using the SSI2144, and linear-controlled VCAs using the SSI2164.
>> 
>> My questions are specifically around using the SSI2140 for pole mixing. From what I can tell, this design is very similar to the filter used in the Matrix-12, and I’ve spent some time studying that schematic. I’ve also reviewed the AN701 filter design document on the Sound Semiconductor website. I’m including my schematic in PDF form in the hope that some of the very smart analog folks here can offer suggestions about something I’m seeing.
>> 
>> I’ve been using Claude.ai <http://claude.ai/> to help analyze each of my filter configurations and determine whether they are behaving as expected. I’ve also been doing sound comparisons against the Arturia Matrix-12 V modeled synth. One thing I’ve found is that I’m getting DC offset that appears to be coming from the pole outputs of the SSI2140. Depending on the pole-mixing resistor configuration selected for a given filter mode, I’m seeing significant DC offset.
>> 
>> I’ve been feeding Claude scope shots to help analyze this, and so far its interpretation seems pretty consistent with what I’m measuring. As a side note, this has been a very useful application of AI for troubleshooting. For the pole-mixing network, I’m using 1% resistors and also using 1% capacitors, as recommended in the data sheet and AN701.
>> 
>> Here is the table Claude generated from my measurements:
>> 
>> Mode    Mean DC Offset
>> LP1     -12.5 mV
>> LP2     -40 mV
>> LP3     -30 mV
>> LP4     -30 mV
>> HP1     -61.9 mV
>> HP2     -131.1 mV
>> HP3     -284.4 mV
>> HP4     -583.6 mV
>> Claude’s current explanation is that the increasing weighting factors in the pole-mixing network are directly amplifying the DC component.
>> 
>> Things that appear to have been ruled out:
>> 
>> Power supply asymmetry (-11.93 V vs. +12.02 V) — likely negligible
>> Input signal DC component — input is about +117 mV, while U1A shows only -8.33 mV offset
>> TL074 op-amp offset voltage — too small to explain this magnitude
>> Unity-gain buffers — not populated - I have jumpers.
>> The suggested fix is to add four 1 µF film capacitors, such as WIMA MKS2 parts, on the SSI2140 OUT1–OUT4 pins, placed between the OUT pins and the 15k mixing resistors. The idea is that this would block DC before it enters the pole-mixing network, preventing it from being amplified by U1B regardless of filter mode.
>> 
>> I’m curious whether adding these coupling capacitors makes sense, and whether that would be compatible with the intended use of the SSI2140. I’m a little surprised that the data sheet does not discuss the need for them if this is expected behavior. I did find some discussion about this on Mod Wiggler, but I didn’t see a clear conclusion.
>> 
>> I’d appreciate any advice, and hopefully I’ll be able to understand it. Also, if you see any other design issues or possible improvements, I’d be grateful for the feedback — pun intended.
>> 
>> Thanks,
>> 
>> Jeff
>> 
>> 
>> 
>> Sent by voice-transit conductor
>> 
>> 
>> 
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