[sdiy] Can anyone read Japanese datasheet

[Richie Burnett]

Thanks for the help, everyone.

> ...the switching edge really does not seem to be specified in that 
> datasheet...

That was the conclusion I arrived at, but wanted to check if there was 
something I missed in the Japanese text.

A bit of background, for anyone interested...

About 35 years ago I was given a Roland SH-09, but it was missing the 
headphone amplifier IC and both DN819 D-type flip-flop ICs for the 
sub-oscillator.  In my youth I lashed something together using a CMOS 4013 
IC and wired that into the place where the two DN819 should have sat on the 
PCB.  The sub-oscillator sprang to life and I thought I had done a 
successful repair all those years ago.  However, one thing always annoyed me 
about that synth...  How the sub-oscillator's pitch trilled between two 
pitches when the pulse wave had fast PWM applied!  Lately I began suspecting 
that my 4013 flip-flops were clocking off the PWM'd edge of the pulse 
waveform, and that the originally intended DN819 ICs clocked off the fixed 
edge of the pulse instead.

The 4013 datasheet states that it is clocked by the rising edge of the clock 
input.  And Don's analysis confirms that the DN819 is clocked off the 
falling edge of the clock input.  So it looks like that is the answer. 
Comparing the service notes for the SH-09 and the SH-101 I see that the '101 
uses a 4013 instead of the rare pair of DN819 chips in the '09.  They also 
put a common-emitted stage ahead of the 4013 to invert the pulse arriving at 
its clock input.  So that is my plan...  I'm going to make a tiny PCB with a 
new surface-mount 4013 accompanied by a SC-70 transistor, a couple of 
resistors to invert the clock and pin headers.  This will fit inside the 
SH-09 where the original DN819s should have sat!  Now I have some confidence 
that it will actually fix the warbling sub-oscillator!

Thanks guys and girls.

-Richie,


-----Original Message----- 
From: Donald Tillman
Sent: Saturday, September 13, 2025 1:50 AM
To: Richie Burnett
Cc: synth-diy mailing list
Subject: Re: [sdiy] Can anyone read Japanese datasheet

Let's see...

Analyzing I2L is weird and error-prone.   Normally you reference the
collector voltages, but no, there are multiple collectors.  So you have to
read the state as whether the transistor is conducting or not.  If you call
not conducting a logical one, then the output is a NAND of the inputs; a
given transistor will conduct (logical zero) only if all of the inputs are
not conducting (logical ones).

Q14 and Q15 are a NAND RS flop.  When the chip clock input is high, Q1 is
conducting, Q9 is conducting, shorting the bases of Q10 and Q12 to ground,
turning them off, leaving Q14 and Q15 to hold their previous value from when
the chip clock input was low.

So I would say the transition happens on the falling edge.  Then Q9 turns
off, the previous value from Q15 goes through Q13 and all, gated by Q10 and
Q12, and stuffed into Q14 and Q15.

Grok and ChatGPT both say rising edge.  Google AI has no idea.

  -- Don
--
Donald Tillman, Palo Alto, California
https://till.com


On Sep 9, 2025, at 12:30 PM, Richie Burnett <rburnett at richieburnett.co.uk>
wrote:


Could someone with Japanese reading skills confirm for me whether the D-type
flip-flop in this attached DN819 datasheet is meant to update it's outputs
on the rising-edge or falling-edge of the clock input?

I tried capturing all of the kanji/hiragana/katakana sections as images and
using Google to translate but still couldn't find this important bit of
information!

Thanks in advance for anyone who is able to help.

-Richie 


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