[sdiy] Can anyone read Japanese datasheet

[Donald Tillman]

Let's see...

Analyzing I2L is weird and error-prone.   Normally you reference the collector voltages, but no, there are multiple collectors.  So you have to read the state as whether the transistor is conducting or not.  If you call not conducting a logical one, then the output is a NAND of the inputs; a given transistor will conduct (logical zero) only if all of the inputs are not conducting (logical ones).

Q14 and Q15 are a NAND RS flop.  When the chip clock input is high, Q1 is conducting, Q9 is conducting, shorting the bases of Q10 and Q12 to ground, turning them off, leaving Q14 and Q15 to hold their previous value from when the chip clock input was low.

So I would say the transition happens on the falling edge.  Then Q9 turns off, the previous value from Q15 goes through Q13 and all, gated by Q10 and Q12, and stuffed into Q14 and Q15.

Grok and ChatGPT both say rising edge.  Google AI has no idea.

  -- Don
--
Donald Tillman, Palo Alto, California
https://till.com

> On Sep 9, 2025, at 12:30 PM, Richie Burnett <rburnett at richieburnett.co.uk> wrote:
> 
> Could someone with Japanese reading skills confirm for me whether the D-type flip-flop in this attached DN819 datasheet is meant to update it's outputs on the rising-edge or falling-edge of the clock input?
> 
> I tried capturing all of the kanji/hiragana/katakana sections as images and using Google to translate but still couldn't find this important bit of information!
> 
> Thanks in advance for anyone who is able to help.
> 
> -Richie
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